/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 79 value is 0. 99 bus-range = <0x00 0xff>; 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | armada-xp-mv78460.dtsi | 65 #size-cells = <0>; 68 cpu@0 { 71 reg = <0>; 72 clocks = <&cpuclk 0>; 103 * MV78460 has 4 PCIe units Gen2.0: Two units can be 116 bus-range = <0x00 0xff>; 119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-xp-mv78260.dtsi | 64 #size-cells = <0>; 67 cpu@0 { 70 reg = <0>; 71 clocks = <&cpuclk 0>; 86 * MV78260 has 3 PCIe units Gen2.0: Two units can be 99 bus-range = <0x00 0xff>; 102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-385.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 45 bus-range = <0x00 0xff>; 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | armada-xp-mv78230.dtsi | 63 #size-cells = <0>; 66 cpu@0 { 69 reg = <0>; 70 clocks = <&cpuclk 0>; 85 * MV78230 has 2 PCIe units Gen2.0: One unit can be 98 bus-range = <0x00 0xff>; 101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ [all …]
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H A D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | kirkwood-98dx4122.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6281.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6192.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | fsl-ls2080a.dtsi | 16 reg = <0x00000000 0x80000000 0 0x80000000>; 22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ 26 interrupts = <1 9 0x4>; 31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 33 <1 11 0x8>, /* Virtual PPI, active-low */ 34 <1 10 0x8>; /* Hypervisor PPI, active-low */ 40 reg = <0x0 0x21c0500 0x0 0x100>; 41 clock-frequency = <0>; /* Updated by bootloader */ [all …]
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-xp-mv78460.dtsi | 28 #size-cells = <0>; 31 cpu@0 { 34 reg = <0>; 35 clocks = <&cpuclk 0>; 66 * MV78460 has 4 PCIe units Gen2.0: Two units can be 79 bus-range = <0x00 0xff>; 82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-xp-mv78260.dtsi | 27 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 34 clocks = <&cpuclk 0>; 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be 62 bus-range = <0x00 0xff>; 65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-385.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 45 bus-range = <0x00 0xff>; 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | armada-xp-mv78230.dtsi | 26 #size-cells = <0>; 29 cpu@0 { 32 reg = <0>; 33 clocks = <&cpuclk 0>; 48 * MV78230 has 2 PCIe units Gen2.0: One unit can be 61 bus-range = <0x00 0xff>; 64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ [all …]
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H A D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | kirkwood-6282.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 23 pcie0: pcie@1,0 { 25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; [all …]
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H A D | armada-39x.dtsi | 32 #size-cells = <0>; 35 cpu@0 { 38 reg = <0>; 59 pcie-mem-aperture = <0xe0000000 0x8000000>; 60 pcie-io-aperture = <0xe8000000 0x100000>; 64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 75 reg = <0x8000 0x1000>; 78 arm,double-linefill-incr = <0>; 79 arm,double-linefill-wrap = <0>; [all …]
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H A D | kirkwood-98dx4122.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6281.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6192.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | armada-370.dtsi | 35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; 47 bus-range = <0x00 0xff>; 50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 57 pcie0: pcie@1,0 { 59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; [all …]
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/openbmc/u-boot/include/configs/ |
H A D | zmx25.h | 23 "gs_fast_boot=setenv bootdelay 5\0" \ 24 "gs_slow_boot=setenv bootdelay 10\0" \ 25 "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ 26 "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ 27 "bootm 0x81000000; bootelf 0x81000000\0" 47 #define CONFIG_FEC_MXC_PHYADDR 0x00 75 #define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ 76 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 79 #define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ 84 #define CONFIG_SYS_FLASH_BASE 0xA0000000 [all …]
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H A D | mx31pdk.h | 28 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 61 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 63 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 64 "bootcmd=run bootcmd_net\0" \ 66 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 67 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 68 "nand erase 0x0 0x40000; " \ 69 "nand write 0x81000000 0x0 0x40000\0" 76 #define CONFIG_SYS_MEMTEST_START 0x80000000 77 #define CONFIG_SYS_MEMTEST_END 0x80010000 [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls2088a.dtsi | 16 cpu0: cpu@0 { 19 reg = <0x0>; 20 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 29 reg = <0x1>; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 39 reg = <0x100>; 49 reg = <0x101>; 59 reg = <0x200>; 69 reg = <0x201>; 79 reg = <0x300>; [all …]
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H A D | fsl-ls2080a.dtsi | 16 cpu0: cpu@0 { 19 reg = <0x0>; 20 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 29 reg = <0x1>; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 39 reg = <0x100>; 49 reg = <0x101>; 59 reg = <0x200>; 69 reg = <0x201>; 79 reg = <0x300>; [all …]
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