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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h21 #define MXS_ICOLL_BASE 0x80000000
22 #define MXS_APBH_BASE 0x80004000
23 #define MXS_ECC8_BASE 0x80008000
24 #define MXS_BCH_BASE 0x8000A000
25 #define MXS_GPMI_BASE 0x8000C000
26 #define MXS_SSP0_BASE 0x80010000
27 #define MXS_SSP1_BASE 0x80034000
28 #define MXS_ETM_BASE 0x80014000
29 #define MXS_PINCTRL_BASE 0x80018000
30 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dgpmi-nand.yaml158 #size-cells = <0>;
160 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
/openbmc/u-boot/include/configs/
H A DBSC9131RDB.h18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
29 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
30 #define CONFIG_SPL_RELOC_STACK 0x00100000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
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H A Dve8313.h33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
[all …]
H A DMPC8323ERDB.h55 #define CONFIG_SYS_SICRL 0x00000000
60 #define CONFIG_SYS_IMMR 0xE0000000
65 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
66 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
67 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
81 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
89 /* 0x80010101 */
90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91 | (0 << TIMING_CFG0_WRT_SHIFT) \
[all …]
H A DMPC832XEMDS.h70 #define CONFIG_SYS_SICRL 0x00000000
75 #define CONFIG_SYS_IMMR 0xE0000000
80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
83 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
89 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
99 /* 0x80840102 */
100 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
101 | (0 << TIMING_CFG0_WRT_SHIFT) \
102 | (0 << TIMING_CFG0_RRT_SHIFT) \
103 | (0 << TIMING_CFG0_WWT_SHIFT) \
[all …]
H A DMPC8569MDS.h52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x00400000
58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
91 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
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H A DBSC9132QDS.h16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
35 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
37 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
38 #define CONFIG_SPL_RELOC_STACK 0x00100000
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
42 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
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H A DMPC8313ERDB.h30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
32 #define CONFIG_SPL_PAD_TO 0x4000
35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
73 #define CONFIG_SYS_IMMR 0xE0000000
79 #define CONFIG_SYS_MEMTEST_START 0x00001000
80 #define CONFIG_SYS_MEMTEST_END 0x07f00000
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
[all …]
H A DMPC8349EMDS.h43 #define CONFIG_SYS_IMMR 0xE0000000
46 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
47 #define CONFIG_SYS_MEMTEST_END 0x00100000
60 #define CONFIG_SYS_SPD_BUS_NUM 0
61 #define SPD_EEPROM_ADDRESS1 0x52
62 #define SPD_EEPROM_ADDRESS2 0x51
66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
90 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
[all …]
H A DUCP1020.h27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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H A Dp1_p2_rdb_pc.h16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
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/openbmc/qemu/hw/mips/
H A Dbootloader.c18 BL_REG_ZERO = 0,
63 stw_p(p, insn >> 0); in st_nm32_p()
73 st_nm32_p(ptr, 0x8000c000); in bl_gen_nop()
77 stl_p(p, 0); in bl_gen_nop()
88 uint32_t insn = 0; in bl_gen_r_type()
95 insn = deposit32(insn, 0, 6, funct); in bl_gen_r_type()
107 uint32_t insn = 0; in bl_gen_i_type()
112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type()
124 bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); in bl_gen_dsll()
133 uint32_t insn = 0; in bl_gen_jalr()
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H A Djazz.c78 address_space_read(&address_space_memory, 0x90000071, in rtc_read()
86 uint8_t buf = val & 0xff; in rtc_write()
87 address_space_write(&address_space_memory, 0x90000071, in rtc_write()
104 return 0xff; in dma_dummy_read()
144 sysbus_mmio_map(sysbus, 0, 0x80001000); in mips_jazz_init_net()
145 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
149 checksum = 0; in mips_jazz_init_net()
150 for (i = 0; i < 6; i++) { in mips_jazz_init_net()
153 if (checksum > 0xff) { in mips_jazz_init_net()
154 checksum = (checksum + 1) & 0xff; in mips_jazz_init_net()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu-v7m.c52 cpu->midr = 0x410cc200; in cortex_m0_initfn()
62 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn()
63 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn()
64 cpu->isar.id_dfr0 = 0x00100000; in cortex_m0_initfn()
65 cpu->id_afr0 = 0x00000000; in cortex_m0_initfn()
66 cpu->isar.id_mmfr0 = 0x00000030; in cortex_m0_initfn()
67 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m0_initfn()
68 cpu->isar.id_mmfr2 = 0x00000000; in cortex_m0_initfn()
69 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m0_initfn()
70 cpu->isar.id_isar0 = 0x01141110; in cortex_m0_initfn()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/openbmc/qemu/hw/arm/
H A Dmusicpal.c43 #define MP_MISC_BASE 0x80002000
44 #define MP_MISC_SIZE 0x00001000
46 #define MP_ETH_BASE 0x80008000
48 #define MP_WLAN_BASE 0x8000C000
49 #define MP_WLAN_SIZE 0x00000800
51 #define MP_UART1_BASE 0x8000C840
52 #define MP_UART2_BASE 0x8000C940
54 #define MP_GPIO_BASE 0x8000D000
55 #define MP_GPIO_SIZE 0x00001000
57 #define MP_FLASHCFG_BASE 0x90006000
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]
/openbmc/qemu/disas/
H A Dnanomips.c62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
123 sizeof(register_list) / sizeof(register_list[0]), info); in decode_gpr_gpr4()
132 * 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
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