Home
last modified time | relevance | path

Searched +full:0 +full:x7f (Results 1 – 25 of 1098) sorted by relevance

12345678910>>...44

/openbmc/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_security.c481 while (pb_addr & 0xFFF) { in gaudi_pb_set_block()
482 WREG32(pb_addr, 0); in gaudi_pb_set_block()
505 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
506 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
507 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
508 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
510 WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
511 WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
513 pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_mme_protection_bits()
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dnv50.c32 /* 0x01: no bank swizzle in nv50_mmu_kind()
33 * 0x02: bank swizzled in nv50_mmu_kind()
34 * 0x7f: invalid in nv50_mmu_kind()
36 * 0x01/0x02 are values understood by the VRAM allocator, in nv50_mmu_kind()
42 0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */ in nv50_mmu_kind()
43 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
44 0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */ in nv50_mmu_kind()
45 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
46 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */ in nv50_mmu_kind()
47 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, in nv50_mmu_kind()
[all …]
/openbmc/linux/drivers/regulator/
H A Drn5t618-regulator.c45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
56 REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000),
[all …]
H A Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
56 .enable_mask = BIT(0), \
60 .qi = BIT(0), \
108 .enable_mask = BIT(0), \
113 .qi = BIT(0), \
152 .enable_mask = BIT(0), \
156 .qi = BIT(0), \
204 .enable_mask = BIT(0), \
209 .qi = BIT(0), \
280 0, 12,
[all …]
H A Drc5t583-regulator.c83 RC5T583_REG(DC0, DC0CTL, 0, DC0CTL, 1, 0x7F, 700, 1500, 12500, 4),
84 RC5T583_REG(DC1, DC1CTL, 0, DC1CTL, 1, 0x7F, 700, 1500, 12500, 14),
85 RC5T583_REG(DC2, DC2CTL, 0, DC2CTL, 1, 0x7F, 900, 2400, 12500, 14),
86 RC5T583_REG(DC3, DC3CTL, 0, DC3CTL, 1, 0x7F, 900, 2400, 12500, 14),
87 RC5T583_REG(LDO0, LDOEN2, 0, LDODIS2, 0, 0x7F, 900, 3400, 25000, 160),
88 RC5T583_REG(LDO1, LDOEN2, 1, LDODIS2, 1, 0x7F, 900, 3400, 25000, 160),
89 RC5T583_REG(LDO2, LDOEN2, 2, LDODIS2, 2, 0x7F, 900, 3400, 25000, 160),
90 RC5T583_REG(LDO3, LDOEN2, 3, LDODIS2, 3, 0x7F, 900, 3400, 25000, 160),
91 RC5T583_REG(LDO4, LDOEN2, 4, LDODIS2, 4, 0x3F, 750, 1500, 12500, 133),
92 RC5T583_REG(LDO5, LDOEN2, 5, LDODIS2, 5, 0x7F, 900, 3400, 25000, 267),
[all …]
H A Dmt6311-regulator.h10 #define MT6311_SWCID 0x01
12 #define MT6311_TOP_INT_CON 0x18
13 #define MT6311_TOP_INT_MON 0x19
15 #define MT6311_VDVFS11_CON0 0x87
16 #define MT6311_VDVFS11_CON7 0x88
17 #define MT6311_VDVFS11_CON8 0x89
18 #define MT6311_VDVFS11_CON9 0x8A
19 #define MT6311_VDVFS11_CON10 0x8B
20 #define MT6311_VDVFS11_CON11 0x8C
21 #define MT6311_VDVFS11_CON12 0x8D
[all …]
H A Dmt6357-regulator.c53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
[all …]
/openbmc/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/openbmc/qemu/tests/tcg/s390x/
H A Dfloat.h13 #define CLASS_MINUS_INF 0
39 /* -inf */ {1, {{0xff, 0x80, 0x00, 0x00}}},
40 /* -Fn */ {2, {{0xc2, 0x28, 0x00, 0x00},
41 {0xc2, 0x29, 0x00, 0x00}}},
42 /* -0 */ {1, {{0x80, 0x00, 0x00, 0x00}}},
43 /* +0 */ {1, {{0x00, 0x00, 0x00, 0x00}}},
44 /* +Fn */ {2, {{0x42, 0x28, 0x00, 0x00},
45 {0x42, 0x2a, 0x00, 0x00}}},
46 /* +inf */ {1, {{0x7f, 0x80, 0x00, 0x00}}},
47 /* QNaN */ {2, {{0x7f, 0xff, 0xff, 0xff},
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/openbmc/u-boot/include/configs/
H A Dhrcon.h77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
83 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
88 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_FSL_SERDES1 0xe3000
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115 /* 0x7b880001 */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
129 /* 0x80010102 */
130 #define CONFIG_SYS_DDR_TIMING_3 0
131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
[all …]
H A Dstrider.h77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
83 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
88 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_FSL_SERDES1 0xe3000
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115 /* 0x7b880001 */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
129 /* 0x80010102 */
130 #define CONFIG_SYS_DDR_TIMING_3 0
131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
[all …]
/openbmc/linux/include/linux/regulator/
H A Dpca9450.h10 PCA9450_TYPE_PCA9450A = 0,
16 PCA9450_BUCK1 = 0,
31 PCA9450_DVS_LEVEL_RUN = 0,
36 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
37 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
44 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Drtl2832_priv.h242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
[all …]
/openbmc/linux/lib/fonts/
H A Dfont_ter16x32.c8 { 0, 0, FONTDATAMAX, 0 }, {
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
11 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
12 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
13 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
14 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
15 0x7f, 0xfc, 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/openbmc/linux/sound/core/seq/
H A Dseq_ump_convert.c37 if (src <= 0x40) in upscale_7_to_16bit()
39 repeat = src & 0x3f; in upscale_7_to_16bit()
48 if (src <= 0x40) in upscale_7_to_32bit()
50 repeat = src & 0x3f; in upscale_7_to_32bit()
60 if (src <= 0x2000) in upscale_14_to_32bit()
62 repeat = src & 0x1fff; in upscale_14_to_32bit()
68 return port->ump_group ? (port->ump_group - 1) : 0; in get_ump_group()
73 ump_compose(type, get_ump_group(port), 0, 0)
122 /* Encoders for MIDI1 status 0x80-0xe0 */
124 {SNDRV_SEQ_EVENT_NOTEOFF, ump_midi1_to_note_ev}, /* 0x80 */
[all …]
/openbmc/linux/drivers/mtd/nand/spi/
H A Desmt.c12 /* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */
13 #define SPINAND_MFR_ESMT_C8 0xc8
16 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
17 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
18 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
19 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
22 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
23 SPINAND_PROG_LOAD(true, 0, NULL, 0));
26 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
27 SPINAND_PROG_LOAD(false, 0, NULL, 0));
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_clamps.S8 movi a2, 0
9 movi a3, 0
13 movi a2, 0x7f
14 movi a3, 0x7f
18 movi a2, 0xffffff80
19 movi a3, 0xffffff80
23 movi a2, 0x80
24 movi a3, 0x7f
28 movi a2, 0xffffff7f
29 movi a3, 0xffffff80
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun8i-di/
H A Dsun8i-di.h20 #define DEINTERLACE_MOD_ENABLE 0x00
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
23 #define DEINTERLACE_FRM_CTRL 0x04
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
30 #define DEINTERLACE_BYPASS 0x08
33 #define DEINTERLACE_AGTH_SEL 0x0c
36 #define DEINTERLACE_LINT_CTRL 0x10
37 #define DEINTERLACE_TRD_PRELUMA 0x1c
38 #define DEINTERLACE_BUF_ADDR0 0x20
39 #define DEINTERLACE_BUF_ADDR1 0x24
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dums512-1h10.dts24 reg = <0x0 0x80000000 0x0 0x80000000>;
45 sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
46 sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>;
47 sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>;
48 sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>;
/openbmc/linux/sound/pci/ice1712/
H A Dwtm.c71 for (id = 0; id < 7; id++) { in stac9460_dac_mute_all()
72 if (*change_mask & (0x01 << id)) { in stac9460_dac_mute_all()
73 if (id == 0) in stac9460_dac_mute_all()
78 new = (~mute << 7 & 0x80) | (old & ~0x80); in stac9460_dac_mute_all()
82 *change_mask = *change_mask | (0x01 << id); in stac9460_dac_mute_all()
84 *change_mask = *change_mask & ~(0x01 << id); in stac9460_dac_mute_all()
90 for (id = 0; id < 3; id++) { in stac9460_dac_mute_all()
91 if (*change_mask & (0x01 << (id + 7))) { in stac9460_dac_mute_all()
92 if (id == 0) in stac9460_dac_mute_all()
97 new = (~mute << 7 & 0x80) | (old & ~0x80); in stac9460_dac_mute_all()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9_smc.h22 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
23 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
24 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
29 u32 setup; /* 0x00 SMC Setup Register */
30 u32 pulse; /* 0x04 SMC Pulse Register */
31 u32 cycle; /* 0x08 SMC Cycle Register */
32 u32 mode; /* 0x0C SMC Mode Register */
41 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
42 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
43 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
[all …]

12345678910>>...44