Lines Matching +full:0 +full:x7f
77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
83 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
88 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_FSL_SERDES1 0xe3000
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115 /* 0x7b880001 */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
129 /* 0x80010102 */
130 #define CONFIG_SYS_DDR_TIMING_3 0
131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
132 | (0 << TIMING_CFG0_WRT_SHIFT) \
133 | (0 << TIMING_CFG0_RRT_SHIFT) \
134 | (0 << TIMING_CFG0_WWT_SHIFT) \
139 /* 0x00260802 */
148 /* 0x26279222 */
149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
156 /* 0x021848c5 */
157 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
158 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
159 /* 0x08240100 */
163 /* 0x43100000 */
165 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
166 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
167 | (0x0242 << SDRAM_MODE_SD_SHIFT))
168 /* ODT 150ohm CL=4, AL=0 on SDRAM */
169 #define CONFIG_SYS_DDR_MODE2 0x00000000
174 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
175 #define CONFIG_SYS_MEMTEST_END 0x07f00000
189 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
190 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
199 #define CONFIG_SYS_LBC_LBCR 0x00040000
210 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
239 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
260 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
274 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
279 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
280 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
288 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
289 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
297 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
300 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
303 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
306 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
312 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
315 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
318 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
321 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
329 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
332 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
335 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
338 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
341 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
344 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
347 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
350 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
355 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
358 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
361 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
364 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
370 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
371 {12, 0x4c} }
375 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
376 {8, 0x4c} }
387 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
388 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
395 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
397 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
398 } while (0)
404 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
411 } while (0)
418 } while (0)
432 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
442 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
443 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
446 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
447 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
448 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
458 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
464 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
473 #define TSEC1_PHYIDX 0
476 /* Options are: eTSEC[0-1] */
485 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
486 #define CONFIG_ENV_SIZE 0x2000
490 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
503 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
520 #define CONFIG_SYS_HID0_INIT 0x000000000
583 "netdev=eth0\0" \
584 "consoledev=ttyS1\0" \
585 "u-boot=u-boot.bin\0" \
586 "kernel_addr=1000000\0" \
587 "fdt_addr=C00000\0" \
588 "fdtfile=hrcon.dtb\0" \
589 "load=tftp ${loadaddr} ${u-boot}\0" \
593 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
594 "upd=run load update\0" \
608 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
609 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \