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Searched +full:0 +full:x71000000 (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dsprd,ums512-glbreg.yaml39 "^clock-controller@[0-9a-f]+$":
55 reg = <0x71000000 0x3000>;
58 ranges = <0 0x71000000 0x3000>;
60 clock-controller@0 {
62 reg = <0x0 0x2000>;
70 reg = <0x32360000 0x1000>;
/openbmc/u-boot/include/configs/
H A Dat91sam9m10g45ek.h38 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
46 #define CONFIG_SYS_SDRAM_BASE 0x70000000
47 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
70 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
73 #define CONFIG_SYS_MEMTEST_END 0x23e00000
77 #define CONFIG_ENV_OFFSET 0x140000
78 #define CONFIG_ENV_OFFSET_REDUND 0x100000
79 #define CONFIG_ENV_SIZE 0x20000
82 "nand read 0x70000000 0x200000 0x300000;" \
83 "bootm 0x70000000"
[all …]
H A Dusbarmory.h20 #define CONFIG_SYS_MMC_ENV_DEV 0
30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
37 #define CONFIG_MXC_USB_FLAGS 0
49 #define CONFIG_LOADADDR 0x72000000
57 "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \
58 "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
61 #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
66 "kernel_addr_r=0x70800000\0" \
67 "fdt_addr_r=0x71000000\0" \
68 "scriptaddr=0x70800000\0" \
[all …]
H A Dsnapper9g45.h30 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \
72 #define CONFIG_SYS_LOAD_ADDR 0x23000000
82 "ethaddr=00:00:00:00:00:00\0" \
83 "serial=0\0" \
84 "stdout=serial_atmel\0" \
85 "stderr=serial_atmel\0" \
86 "stdin=serial_atmel\0" \
87 "bootlimit=3\0" \
88 "loadaddr=0x71000000\0" \
89 "board_rev=2\0" \
[all …]
H A Dmx53loco.h31 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
38 #define CONFIG_FEC_MXC_PHYADDR 0x1F
44 #define CONFIG_MXC_USB_FLAGS 0
59 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
60 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
70 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
73 "script=boot.scr\0" \
74 "image=zImage\0" \
75 "fdt_addr=0x71000000\0" \
76 "boot_fdt=try\0" \
[all …]
H A DM5485EVB.h22 #define CONFIG_SYS_UART_PORT (0)
40 # define CONFIG_SYS_FEC0_PINMUX 0
42 # define CONFIG_SYS_FEC1_PINMUX 0
66 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
84 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
86 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
88 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
90 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
[all …]
H A DM5475EVB.h22 #define CONFIG_SYS_UART_PORT (0)
40 # define CONFIG_SYS_FEC0_PINMUX 0
42 # define CONFIG_SYS_FEC1_PINMUX 0
79 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
80 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
89 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
91 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
93 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
95 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
97 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
/openbmc/u-boot/configs/
H A Dm53menlo_defconfig3 CONFIG_SYS_TEXT_BASE=0x71000000
52 CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
53 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
/openbmc/qemu/hw/sparc/
H A Dsun4m.c74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_VADDR 0xffd00000
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { in DECLARE_CLASS_CHECKERS()
142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); in fw_cfg_boot_set()
[all …]
/openbmc/qemu/hw/ppc/
H A Dspapr_vio.c42 #define SPAPR_VIO_REG_BASE 0x71000000
92 if (vdevice_off < 0) { in vio_make_devnode()
99 if (node_off < 0) { in vio_make_devnode()
104 if (ret < 0) { in vio_make_devnode()
111 if (ret < 0) { in vio_make_devnode()
125 if (ret < 0) { in vio_make_devnode()
136 if (ret < 0) { in vio_make_devnode()
142 if (ret < 0) { in vio_make_devnode()
148 if (ret < 0) { in vio_make_devnode()
162 target_ulong reg = args[0]; in h_reg_crq()
[all …]
/openbmc/linux/drivers/mfd/
H A Docelot-spi.c30 #define REG_DEV_CPUORG_IF_CTRL 0x0000
31 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
33 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
38 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
41 #define VSC7512_CHIP_REGS_RES_START 0x71070000
42 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
[all …]
/openbmc/linux/drivers/misc/cb710/
H A Dcore.c31 unsigned int devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); in cb710_pci_configure()
35 cb710_pci_update_config_reg(pdev, 0x48, in cb710_pci_configure()
36 ~0x000000FF, 0x0000003F); in cb710_pci_configure()
38 pci_read_config_dword(pdev, 0x48, &val); in cb710_pci_configure()
39 if (val & 0x80000000) in cb710_pci_configure()
40 return 0; in cb710_pci_configure()
48 cb710_pci_update_config_reg(pdev0, 0x8C, in cb710_pci_configure()
49 ~0x00F00000, 0x00100000); in cb710_pci_configure()
50 cb710_pci_update_config_reg(pdev0, 0xB0, in cb710_pci_configure()
51 ~0x08000000, 0x08000000); in cb710_pci_configure()
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/drivers/clk/sprd/
H A Dums512-clk.c33 static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0);
34 static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0);
35 static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0);
36 static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0);
37 static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0);
38 static CLK_FIXED_FACTOR_FW_NAME(clk_1m, "clk-1m", "ext-26m", 26, 1, 0);
39 static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0);
40 static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0);
41 static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0);
42 static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0);
[all …]
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc20 QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
71 tcg_debug_assert(slot >= 0 && slot <= 1);
87 if (offset == sextract64(offset, 0, 26)) {
90 *src_rw = deposit32(*src_rw, 0, 26, offset);
101 if (offset == sextract64(offset, 0, 19)) {
113 if (offset == sextract64(offset, 0, 14)) {
123 tcg_debug_assert(addend == 0);
137 #define TCG_CT_CONST_AIMM 0x100
138 #define TCG_CT_CONST_LIMM 0x200
139 #define TCG_CT_CONST_ZERO 0x400
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]