1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23bf801a2SAndrej Rosano /* 33bf801a2SAndrej Rosano * USB armory MkI board configuration settings 43bf801a2SAndrej Rosano * http://inversepath.com/usbarmory 53bf801a2SAndrej Rosano * 63bf801a2SAndrej Rosano * Copyright (C) 2015, Inverse Path 73bf801a2SAndrej Rosano * Andrej Rosano <andrej@inversepath.com> 83bf801a2SAndrej Rosano */ 93bf801a2SAndrej Rosano 103bf801a2SAndrej Rosano #ifndef __CONFIG_H 113bf801a2SAndrej Rosano #define __CONFIG_H 123bf801a2SAndrej Rosano 1318fb0e3cSGong Qianyu #define CONFIG_SYS_FSL_CLK 143bf801a2SAndrej Rosano 153bf801a2SAndrej Rosano #include <asm/arch/imx-regs.h> 163bf801a2SAndrej Rosano 173bf801a2SAndrej Rosano /* U-Boot environment */ 183bf801a2SAndrej Rosano #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 193bf801a2SAndrej Rosano #define CONFIG_ENV_SIZE (8 * 1024) 203bf801a2SAndrej Rosano #define CONFIG_SYS_MMC_ENV_DEV 0 213bf801a2SAndrej Rosano 223bf801a2SAndrej Rosano /* U-Boot general configurations */ 233bf801a2SAndrej Rosano #define CONFIG_SYS_CBSIZE 512 243bf801a2SAndrej Rosano 253bf801a2SAndrej Rosano /* UART */ 263bf801a2SAndrej Rosano #define CONFIG_MXC_UART 273bf801a2SAndrej Rosano #define CONFIG_MXC_UART_BASE UART1_BASE 283bf801a2SAndrej Rosano 293bf801a2SAndrej Rosano /* SD/MMC */ 303bf801a2SAndrej Rosano #define CONFIG_SYS_FSL_ESDHC_ADDR 0 313bf801a2SAndrej Rosano #define CONFIG_SYS_FSL_ESDHC_NUM 1 323bf801a2SAndrej Rosano 333bf801a2SAndrej Rosano /* USB */ 343bf801a2SAndrej Rosano #define CONFIG_USB_EHCI_MX5 353bf801a2SAndrej Rosano #define CONFIG_MXC_USB_PORT 1 363bf801a2SAndrej Rosano #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 373bf801a2SAndrej Rosano #define CONFIG_MXC_USB_FLAGS 0 383bf801a2SAndrej Rosano 393bf801a2SAndrej Rosano /* I2C */ 403bf801a2SAndrej Rosano #define CONFIG_SYS_I2C 413bf801a2SAndrej Rosano #define CONFIG_SYS_I2C_MXC 4203544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 4303544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 443bf801a2SAndrej Rosano 453bf801a2SAndrej Rosano /* Fuse */ 463bf801a2SAndrej Rosano #define CONFIG_FSL_IIM 473bf801a2SAndrej Rosano 489a45ec3eSAndrej Rosano /* U-Boot memory offsets */ 493bf801a2SAndrej Rosano #define CONFIG_LOADADDR 0x72000000 503bf801a2SAndrej Rosano #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 519a45ec3eSAndrej Rosano 529a45ec3eSAndrej Rosano /* Linux boot */ 535bc0543dSMario Six #define CONFIG_HOSTNAME "usbarmory" 543bf801a2SAndrej Rosano #define CONFIG_BOOTCOMMAND \ 553bf801a2SAndrej Rosano "run distro_bootcmd; " \ 563bf801a2SAndrej Rosano "setenv bootargs console=${console} ${bootargs_default}; " \ 579a45ec3eSAndrej Rosano "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \ 583bf801a2SAndrej Rosano "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ 599a45ec3eSAndrej Rosano "bootz ${kernel_addr_r} - ${fdt_addr_r}" 603bf801a2SAndrej Rosano 613bf801a2SAndrej Rosano #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) 623bf801a2SAndrej Rosano 633bf801a2SAndrej Rosano #include <config_distro_bootcmd.h> 643bf801a2SAndrej Rosano 653bf801a2SAndrej Rosano #define MEM_LAYOUT_ENV_SETTINGS \ 663bf801a2SAndrej Rosano "kernel_addr_r=0x70800000\0" \ 673bf801a2SAndrej Rosano "fdt_addr_r=0x71000000\0" \ 683bf801a2SAndrej Rosano "scriptaddr=0x70800000\0" \ 693bf801a2SAndrej Rosano "pxefile_addr_r=0x70800000\0" \ 703bf801a2SAndrej Rosano "ramdisk_addr_r=0x73000000\0" 713bf801a2SAndrej Rosano 723bf801a2SAndrej Rosano #define CONFIG_EXTRA_ENV_SETTINGS \ 733bf801a2SAndrej Rosano MEM_LAYOUT_ENV_SETTINGS \ 743bf801a2SAndrej Rosano "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ 753bf801a2SAndrej Rosano "fdtfile=imx53-usbarmory.dtb\0" \ 763bf801a2SAndrej Rosano "console=ttymxc0,115200\0" \ 773bf801a2SAndrej Rosano BOOTENV 783bf801a2SAndrej Rosano 79a02ab5eaSAndrej Rosano #ifndef CONFIG_CMDLINE 80a02ab5eaSAndrej Rosano #define USBARMORY_FIT_PATH "/boot/usbarmory.itb" 81a02ab5eaSAndrej Rosano #define USBARMORY_FIT_ADDR "0x70800000" 82a02ab5eaSAndrej Rosano #endif 83a02ab5eaSAndrej Rosano 843bf801a2SAndrej Rosano /* Physical Memory Map */ 853bf801a2SAndrej Rosano #define PHYS_SDRAM CSD0_BASE_ADDR 863bf801a2SAndrej Rosano #define PHYS_SDRAM_SIZE (gd->ram_size) 873bf801a2SAndrej Rosano 883bf801a2SAndrej Rosano #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 893bf801a2SAndrej Rosano #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 903bf801a2SAndrej Rosano #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 913bf801a2SAndrej Rosano 923bf801a2SAndrej Rosano #define CONFIG_SYS_INIT_SP_OFFSET \ 933bf801a2SAndrej Rosano (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 943bf801a2SAndrej Rosano #define CONFIG_SYS_INIT_SP_ADDR \ 953bf801a2SAndrej Rosano (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 963bf801a2SAndrej Rosano 973bf801a2SAndrej Rosano #define CONFIG_SYS_MEMTEST_START 0x70000000 983bf801a2SAndrej Rosano #define CONFIG_SYS_MEMTEST_END 0x90000000 993bf801a2SAndrej Rosano 1003bf801a2SAndrej Rosano #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 1013bf801a2SAndrej Rosano 1023bf801a2SAndrej Rosano #endif /* __CONFIG_H */ 103