1f3e89362SColin Foster // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2f3e89362SColin Foster /*
3f3e89362SColin Foster * SPI core driver for the Ocelot chip family.
4f3e89362SColin Foster *
5f3e89362SColin Foster * This driver will handle everything necessary to allow for communication over
6f3e89362SColin Foster * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
7f3e89362SColin Foster * are to prepare the chip's SPI interface for a specific bus speed, and a host
8f3e89362SColin Foster * processor's endianness. This will create and distribute regmaps for any
9f3e89362SColin Foster * children.
10f3e89362SColin Foster *
11f3e89362SColin Foster * Copyright 2021-2022 Innovative Advantage Inc.
12f3e89362SColin Foster *
13f3e89362SColin Foster * Author: Colin Foster <colin.foster@in-advantage.com>
14f3e89362SColin Foster */
15f3e89362SColin Foster
16f3e89362SColin Foster #include <linux/device.h>
17f3e89362SColin Foster #include <linux/err.h>
18f3e89362SColin Foster #include <linux/errno.h>
19f3e89362SColin Foster #include <linux/export.h>
20f3e89362SColin Foster #include <linux/ioport.h>
21f3e89362SColin Foster #include <linux/mod_devicetable.h>
22f3e89362SColin Foster #include <linux/module.h>
23f3e89362SColin Foster #include <linux/regmap.h>
24f3e89362SColin Foster #include <linux/spi/spi.h>
25f3e89362SColin Foster #include <linux/types.h>
26f3e89362SColin Foster #include <linux/units.h>
27f3e89362SColin Foster
28f3e89362SColin Foster #include "ocelot.h"
29f3e89362SColin Foster
30f3e89362SColin Foster #define REG_DEV_CPUORG_IF_CTRL 0x0000
31f3e89362SColin Foster #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
32f3e89362SColin Foster
33f3e89362SColin Foster #define CFGSTAT_IF_NUM_VCORE (0 << 24)
34f3e89362SColin Foster #define CFGSTAT_IF_NUM_VRAP (1 << 24)
35f3e89362SColin Foster #define CFGSTAT_IF_NUM_SI (2 << 24)
36f3e89362SColin Foster #define CFGSTAT_IF_NUM_MIIM (3 << 24)
37f3e89362SColin Foster
38f3e89362SColin Foster #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39f3e89362SColin Foster #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
40f3e89362SColin Foster
41f3e89362SColin Foster #define VSC7512_CHIP_REGS_RES_START 0x71070000
42f3e89362SColin Foster #define VSC7512_CHIP_REGS_RES_SIZE 0x14
43f3e89362SColin Foster
44f3e89362SColin Foster static const struct resource vsc7512_dev_cpuorg_resource =
45f3e89362SColin Foster DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
46f3e89362SColin Foster VSC7512_DEVCPU_ORG_RES_SIZE,
47f3e89362SColin Foster "devcpu_org");
48f3e89362SColin Foster
49f3e89362SColin Foster static const struct resource vsc7512_gcb_resource =
50f3e89362SColin Foster DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
51f3e89362SColin Foster VSC7512_CHIP_REGS_RES_SIZE,
52f3e89362SColin Foster "devcpu_gcb_chip_regs");
53f3e89362SColin Foster
ocelot_spi_initialize(struct device * dev)54f3e89362SColin Foster static int ocelot_spi_initialize(struct device *dev)
55f3e89362SColin Foster {
56f3e89362SColin Foster struct ocelot_ddata *ddata = dev_get_drvdata(dev);
57f3e89362SColin Foster u32 val, check;
58f3e89362SColin Foster int err;
59f3e89362SColin Foster
60f3e89362SColin Foster val = OCELOT_SPI_BYTE_ORDER;
61f3e89362SColin Foster
62f3e89362SColin Foster /*
63f3e89362SColin Foster * The SPI address must be big-endian, but we want the payload to match
64f3e89362SColin Foster * our CPU. These are two bits (0 and 1) but they're repeated such that
65f3e89362SColin Foster * the write from any configuration will be valid. The four
66f3e89362SColin Foster * configurations are:
67f3e89362SColin Foster *
68f3e89362SColin Foster * 0b00: little-endian, MSB first
69f3e89362SColin Foster * | 111111 | 22221111 | 33222222 |
70f3e89362SColin Foster * | 76543210 | 54321098 | 32109876 | 10987654 |
71f3e89362SColin Foster *
72f3e89362SColin Foster * 0b01: big-endian, MSB first
73f3e89362SColin Foster * | 33222222 | 22221111 | 111111 | |
74f3e89362SColin Foster * | 10987654 | 32109876 | 54321098 | 76543210 |
75f3e89362SColin Foster *
76f3e89362SColin Foster * 0b10: little-endian, LSB first
77f3e89362SColin Foster * | 111111 | 11112222 | 22222233 |
78f3e89362SColin Foster * | 01234567 | 89012345 | 67890123 | 45678901 |
79f3e89362SColin Foster *
80f3e89362SColin Foster * 0b11: big-endian, LSB first
81f3e89362SColin Foster * | 22222233 | 11112222 | 111111 | |
82f3e89362SColin Foster * | 45678901 | 67890123 | 89012345 | 01234567 |
83f3e89362SColin Foster */
84f3e89362SColin Foster err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
85f3e89362SColin Foster if (err)
86f3e89362SColin Foster return err;
87f3e89362SColin Foster
88f3e89362SColin Foster /*
89f3e89362SColin Foster * Apply the number of padding bytes between a read request and the data
90f3e89362SColin Foster * payload. Some registers have access times of up to 1us, so if the
91f3e89362SColin Foster * first payload bit is shifted out too quickly, the read will fail.
92f3e89362SColin Foster */
93f3e89362SColin Foster val = ddata->spi_padding_bytes;
94f3e89362SColin Foster err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
95f3e89362SColin Foster if (err)
96f3e89362SColin Foster return err;
97f3e89362SColin Foster
98f3e89362SColin Foster /*
99f3e89362SColin Foster * After we write the interface configuration, read it back here. This
100f3e89362SColin Foster * will verify several different things. The first is that the number of
101f3e89362SColin Foster * padding bytes actually got written correctly. These are found in bits
102f3e89362SColin Foster * 0:3.
103f3e89362SColin Foster *
104f3e89362SColin Foster * The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
105f3e89362SColin Foster * and will be set if the register access is too fast. This would be in
106f3e89362SColin Foster * the condition that the number of padding bytes is insufficient for
107f3e89362SColin Foster * the SPI bus frequency.
108f3e89362SColin Foster *
109f3e89362SColin Foster * The last check is for bits 31:24, which define the interface by which
110f3e89362SColin Foster * the registers are being accessed. Since we're accessing them via the
111f3e89362SColin Foster * serial interface, it must return IF_NUM_SI.
112f3e89362SColin Foster */
113f3e89362SColin Foster check = val | CFGSTAT_IF_NUM_SI;
114f3e89362SColin Foster
115f3e89362SColin Foster err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
116f3e89362SColin Foster if (err)
117f3e89362SColin Foster return err;
118f3e89362SColin Foster
119f3e89362SColin Foster if (check != val)
120f3e89362SColin Foster return -ENODEV;
121f3e89362SColin Foster
122f3e89362SColin Foster return 0;
123f3e89362SColin Foster }
124f3e89362SColin Foster
125f3e89362SColin Foster static const struct regmap_config ocelot_spi_regmap_config = {
126f3e89362SColin Foster .reg_bits = 24,
127f3e89362SColin Foster .reg_stride = 4,
128f3e89362SColin Foster .reg_shift = REGMAP_DOWNSHIFT(2),
129f3e89362SColin Foster .val_bits = 32,
130f3e89362SColin Foster
131f3e89362SColin Foster .write_flag_mask = 0x80,
132f3e89362SColin Foster
133*f0484d2fSColin Foster .use_single_read = true,
134f3e89362SColin Foster .use_single_write = true,
135f3e89362SColin Foster .can_multi_write = false,
136f3e89362SColin Foster
137f3e89362SColin Foster .reg_format_endian = REGMAP_ENDIAN_BIG,
138f3e89362SColin Foster .val_format_endian = REGMAP_ENDIAN_NATIVE,
139f3e89362SColin Foster };
140f3e89362SColin Foster
ocelot_spi_regmap_bus_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)141f3e89362SColin Foster static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
142f3e89362SColin Foster void *val, size_t val_size)
143f3e89362SColin Foster {
144f3e89362SColin Foster struct spi_transfer xfers[3] = {0};
145f3e89362SColin Foster struct device *dev = context;
146f3e89362SColin Foster struct ocelot_ddata *ddata;
147f3e89362SColin Foster struct spi_device *spi;
148f3e89362SColin Foster struct spi_message msg;
149f3e89362SColin Foster unsigned int index = 0;
150f3e89362SColin Foster
151f3e89362SColin Foster ddata = dev_get_drvdata(dev);
152f3e89362SColin Foster spi = to_spi_device(dev);
153f3e89362SColin Foster
154f3e89362SColin Foster xfers[index].tx_buf = reg;
155f3e89362SColin Foster xfers[index].len = reg_size;
156f3e89362SColin Foster index++;
157f3e89362SColin Foster
158f3e89362SColin Foster if (ddata->spi_padding_bytes) {
159f3e89362SColin Foster xfers[index].len = ddata->spi_padding_bytes;
160f3e89362SColin Foster xfers[index].tx_buf = ddata->dummy_buf;
161f3e89362SColin Foster xfers[index].dummy_data = 1;
162f3e89362SColin Foster index++;
163f3e89362SColin Foster }
164f3e89362SColin Foster
165f3e89362SColin Foster xfers[index].rx_buf = val;
166f3e89362SColin Foster xfers[index].len = val_size;
167f3e89362SColin Foster index++;
168f3e89362SColin Foster
169f3e89362SColin Foster spi_message_init_with_transfers(&msg, xfers, index);
170f3e89362SColin Foster
171f3e89362SColin Foster return spi_sync(spi, &msg);
172f3e89362SColin Foster }
173f3e89362SColin Foster
ocelot_spi_regmap_bus_write(void * context,const void * data,size_t count)174f3e89362SColin Foster static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
175f3e89362SColin Foster {
176f3e89362SColin Foster struct device *dev = context;
177f3e89362SColin Foster struct spi_device *spi = to_spi_device(dev);
178f3e89362SColin Foster
179f3e89362SColin Foster return spi_write(spi, data, count);
180f3e89362SColin Foster }
181f3e89362SColin Foster
182f3e89362SColin Foster static const struct regmap_bus ocelot_spi_regmap_bus = {
183f3e89362SColin Foster .write = ocelot_spi_regmap_bus_write,
184f3e89362SColin Foster .read = ocelot_spi_regmap_bus_read,
185f3e89362SColin Foster };
186f3e89362SColin Foster
ocelot_spi_init_regmap(struct device * dev,const struct resource * res)187f3e89362SColin Foster struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
188f3e89362SColin Foster {
189f3e89362SColin Foster struct regmap_config regmap_config;
190f3e89362SColin Foster
191f3e89362SColin Foster memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
192f3e89362SColin Foster
193f3e89362SColin Foster regmap_config.name = res->name;
194f3e89362SColin Foster regmap_config.max_register = resource_size(res) - 1;
195f3e89362SColin Foster regmap_config.reg_base = res->start;
196f3e89362SColin Foster
197f3e89362SColin Foster return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config);
198f3e89362SColin Foster }
199f3e89362SColin Foster EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
200f3e89362SColin Foster
ocelot_spi_probe(struct spi_device * spi)201f3e89362SColin Foster static int ocelot_spi_probe(struct spi_device *spi)
202f3e89362SColin Foster {
203f3e89362SColin Foster struct device *dev = &spi->dev;
204f3e89362SColin Foster struct ocelot_ddata *ddata;
205f3e89362SColin Foster struct regmap *r;
206f3e89362SColin Foster int err;
207f3e89362SColin Foster
208f3e89362SColin Foster ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
209f3e89362SColin Foster if (!ddata)
210f3e89362SColin Foster return -ENOMEM;
211f3e89362SColin Foster
212f3e89362SColin Foster spi_set_drvdata(spi, ddata);
213f3e89362SColin Foster
214f3e89362SColin Foster if (spi->max_speed_hz <= 500000) {
215f3e89362SColin Foster ddata->spi_padding_bytes = 0;
216f3e89362SColin Foster } else {
217f3e89362SColin Foster /*
218f3e89362SColin Foster * Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
219f3e89362SColin Foster * Register access time is 1us, so we need to configure and send
220f3e89362SColin Foster * out enough padding bytes between the read request and data
221f3e89362SColin Foster * transmission that lasts at least 1 microsecond.
222f3e89362SColin Foster */
223f3e89362SColin Foster ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
224f3e89362SColin Foster
225f3e89362SColin Foster ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
226f3e89362SColin Foster if (!ddata->dummy_buf)
227f3e89362SColin Foster return -ENOMEM;
228f3e89362SColin Foster }
229f3e89362SColin Foster
230f3e89362SColin Foster spi->bits_per_word = 8;
231f3e89362SColin Foster
232f3e89362SColin Foster err = spi_setup(spi);
233f3e89362SColin Foster if (err)
234f3e89362SColin Foster return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
235f3e89362SColin Foster
236f3e89362SColin Foster r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
237f3e89362SColin Foster if (IS_ERR(r))
238f3e89362SColin Foster return PTR_ERR(r);
239f3e89362SColin Foster
240f3e89362SColin Foster ddata->cpuorg_regmap = r;
241f3e89362SColin Foster
242f3e89362SColin Foster r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
243f3e89362SColin Foster if (IS_ERR(r))
244f3e89362SColin Foster return PTR_ERR(r);
245f3e89362SColin Foster
246f3e89362SColin Foster ddata->gcb_regmap = r;
247f3e89362SColin Foster
248f3e89362SColin Foster /*
249f3e89362SColin Foster * The chip must be set up for SPI before it gets initialized and reset.
250f3e89362SColin Foster * This must be done before calling init, and after a chip reset is
251f3e89362SColin Foster * performed.
252f3e89362SColin Foster */
253f3e89362SColin Foster err = ocelot_spi_initialize(dev);
254f3e89362SColin Foster if (err)
255f3e89362SColin Foster return dev_err_probe(dev, err, "Error initializing SPI bus\n");
256f3e89362SColin Foster
257f3e89362SColin Foster err = ocelot_chip_reset(dev);
258f3e89362SColin Foster if (err)
259f3e89362SColin Foster return dev_err_probe(dev, err, "Error resetting device\n");
260f3e89362SColin Foster
261f3e89362SColin Foster /*
262f3e89362SColin Foster * A chip reset will clear the SPI configuration, so it needs to be done
263f3e89362SColin Foster * again before we can access any registers.
264f3e89362SColin Foster */
265f3e89362SColin Foster err = ocelot_spi_initialize(dev);
266f3e89362SColin Foster if (err)
267f3e89362SColin Foster return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
268f3e89362SColin Foster
269f3e89362SColin Foster err = ocelot_core_init(dev);
270f3e89362SColin Foster if (err)
271f3e89362SColin Foster return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
272f3e89362SColin Foster
273f3e89362SColin Foster return 0;
274f3e89362SColin Foster }
275f3e89362SColin Foster
276f3e89362SColin Foster static const struct spi_device_id ocelot_spi_ids[] = {
277f3e89362SColin Foster { "vsc7512", 0 },
278f3e89362SColin Foster { }
279f3e89362SColin Foster };
28002010cf0SYang Yingliang MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
281f3e89362SColin Foster
282f3e89362SColin Foster static const struct of_device_id ocelot_spi_of_match[] = {
283f3e89362SColin Foster { .compatible = "mscc,vsc7512" },
284f3e89362SColin Foster { }
285f3e89362SColin Foster };
286f3e89362SColin Foster MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
287f3e89362SColin Foster
288f3e89362SColin Foster static struct spi_driver ocelot_spi_driver = {
289f3e89362SColin Foster .driver = {
290f3e89362SColin Foster .name = "ocelot-soc",
291f3e89362SColin Foster .of_match_table = ocelot_spi_of_match,
292f3e89362SColin Foster },
293f3e89362SColin Foster .id_table = ocelot_spi_ids,
294f3e89362SColin Foster .probe = ocelot_spi_probe,
295f3e89362SColin Foster };
296f3e89362SColin Foster module_spi_driver(ocelot_spi_driver);
297f3e89362SColin Foster
298f3e89362SColin Foster MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
299f3e89362SColin Foster MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
300f3e89362SColin Foster MODULE_LICENSE("Dual MIT/GPL");
301f3e89362SColin Foster MODULE_IMPORT_NS(MFD_OCELOT);
302