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/openbmc/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
41 "^reset-controller@[0-9a-f]+$":
44 "^regulator@[0-9a-f]+$":
47 "^phy@[0-9a-f]+$":
62 reg = <0x65b00000 0x400>;
65 ranges = <0 0x65b00000 0x400>;
67 reset-controller@0 {
69 reg = <0x0 0x4>;
[all …]
H A Dsocionext,uniphier-ahci-glue.yaml37 "^reset-controller@[0-9a-f]+$":
40 "phy@[0-9a-f]+$":
53 reg = <0x65b00000 0x400>;
56 ranges = <0 0x65700000 0x100>;
58 reset-controller@0 {
60 reg = <0x0 0x4>;
70 reg = <0x10 0x10>;
75 #phy-cells = <0>;
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
[all …]
H A Duniphier-pxs3.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
52 reg = <0 0x001>;
61 reg = <0 0x002>;
70 reg = <0 0x003>;
123 #clock-cells = <0>;
141 soc@0 {
145 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 <0x506c0000 0x400>;
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld20.dtsi12 /memreserve/ 0x80000000 0x02000000;
22 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0 0x000>;
57 reg = <0 0x001>;
67 reg = <0 0x100>;
77 reg = <0 0x101>;
169 #clock-cells = <0>;
221 soc@0 {
225 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]