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/openbmc/linux/arch/m68k/include/asm/
H A Dsun3x.h6 #define SUN3X_IOMMU 0x60000000
7 #define SUN3X_ENAREG 0x61000000
8 #define SUN3X_INTREG 0x61001400
9 #define SUN3X_DIAGREG 0x61001800
10 #define SUN3X_ZS1 0x62000000
11 #define SUN3X_ZS2 0x62002000
12 #define SUN3X_LANCE 0x65002000
13 #define SUN3X_EEPROM 0x64000000
14 #define SUN3X_IDPROM 0x640007d8
15 #define SUN3X_VIDEO_BASE 0x50000000
[all …]
H A Dsun3xprom.h18 #define SUN3X_IOMMU 0x60000000
19 #define SUN3X_ENAREG 0x61000000
20 #define SUN3X_INTREG 0x61001400
21 #define SUN3X_DIAGREG 0x61001800
22 #define SUN3X_ZS1 0x62000000
23 #define SUN3X_ZS2 0x62002000
24 #define SUN3X_LANCE 0x65002000
25 #define SUN3X_EEPROM 0x64000000
26 #define SUN3X_IDPROM 0x640007d8
27 #define SUN3X_VIDEO_BASE 0x50400000
[all …]
/openbmc/u-boot/include/configs/
H A Drv1108_common.h17 #define CONFIG_SYS_TIMER_BASE 0x10350020
20 #define CONFIG_SYS_SDRAM_BASE 0x60000000
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
22 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
31 "scriptaddr=0x60000000\0" \
32 "fdt_addr_r=0x61f00000\0" \
33 "kernel_addr_r=0x62000000\0" \
34 "ramdisk_addr_r=0x64000000\0"
39 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
H A Drk3128_common.h18 #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
21 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
22 #define CONFIG_SYS_LOAD_ADDR 0x60800800
30 #define CONFIG_SYS_SDRAM_BASE 0x60000000
31 #define SDRAM_MAX_SIZE 0x80000000
41 "scriptaddr=0x60500000\0" \
42 "pxefile_addr_r=0x60600000\0" \
43 "fdt_addr_r=0x61f00000\0" \
44 "kernel_addr_r=0x62000000\0" \
45 "ramdisk_addr_r=0x64000000\0"
[all …]
H A Drk3036_common.h16 #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
19 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
20 #define CONFIG_SYS_LOAD_ADDR 0x60800800
21 #define CONFIG_SPL_STACK 0x10081fff
22 #define CONFIG_SPL_TEXT_BASE 0x10081000
27 #define CONFIG_SYS_SDRAM_BASE 0x60000000
41 "scriptaddr=0x60000000\0" \
42 "pxefile_addr_r=0x60100000\0" \
43 "fdt_addr_r=0x61f00000\0" \
44 "kernel_addr_r=0x62000000\0" \
[all …]
H A Drk3188_common.h21 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
23 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
24 #define CONFIG_SYS_LOAD_ADDR 0x60800800
26 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
29 #define CONFIG_SPL_TEXT_BASE 0x10080800
31 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
34 #define CONFIG_SPL_STACK 0x10087fff
36 #define CONFIG_SYS_SDRAM_BASE 0x60000000
38 #define SDRAM_MAX_SIZE 0x80000000
45 "scriptaddr=0x60000000\0" \
[all …]
H A Drk322x_common.h17 #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
20 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
21 #define CONFIG_SYS_LOAD_ADDR 0x60800800
22 #define CONFIG_SPL_STACK 0x10088000
23 #define CONFIG_SPL_TEXT_BASE 0x10081000
28 #define CONFIG_SYS_SDRAM_BASE 0x60000000
30 #define SDRAM_MAX_SIZE 0x80000000
40 "scriptaddr=0x60000000\0" \
41 "pxefile_addr_r=0x60100000\0" \
42 "fdt_addr_r=0x61f00000\0" \
[all …]
H A Dve8313.h33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi.yaml46 <bank-number> 0 <address of the bank> <size>
49 "^.*@[0-4],[a-f0-9]+$":
73 reg = <0x58002000 0x1000>;
77 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
78 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
79 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
80 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
81 <4 0 0x80000000 0x10000000>; /* NAND */
83 psram@0,0 {
85 reg = <0 0x00000000 0x100000>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Daccel.c19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
35 return 0; in viafb_set_bpp()
44 u32 ge_cmd = 0, tmp, i; in hw_bitblt_1()
54 ge_cmd |= 0x00008000; in hw_bitblt_1()
59 ge_cmd |= 0x00004000; in hw_bitblt_1()
67 case 0x00: /* blackness */ in hw_bitblt_1()
68 case 0x5A: /* pattern inversion */ in hw_bitblt_1()
69 case 0xF0: /* pattern copy */ in hw_bitblt_1()
70 case 0xFF: /* whiteness */ in hw_bitblt_1()
84 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000) in hw_bitblt_1()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dowl-mmc.c28 #define OWL_REG_SD_EN 0x0000
29 #define OWL_REG_SD_CTL 0x0004
30 #define OWL_REG_SD_STATE 0x0008
31 #define OWL_REG_SD_CMD 0x000c
32 #define OWL_REG_SD_ARG 0x0010
33 #define OWL_REG_SD_RSPBUF0 0x0014
34 #define OWL_REG_SD_RSPBUF1 0x0018
35 #define OWL_REG_SD_RSPBUF2 0x001c
36 #define OWL_REG_SD_RSPBUF3 0x0020
37 #define OWL_REG_SD_RSPBUF4 0x0024
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c15 #define GPIO_BASE_ADDR 0x48000000
16 #define GPIO_SIZE 0x400
20 #define GPIO_A 0x48000000
21 #define GPIO_B 0x48000400
22 #define GPIO_C 0x48000800
23 #define GPIO_D 0x48000C00
24 #define GPIO_E 0x48001000
25 #define GPIO_F 0x48001400
26 #define GPIO_G 0x48001800
27 #define GPIO_H 0x48001C00
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_srv.c72 #define DMUB_CW0_BASE (0x60000000)
73 #define DMUB_CW1_BASE (0x61000000)
74 #define DMUB_CW3_BASE (0x63000000)
75 #define DMUB_CW4_BASE (0x64000000)
76 #define DMUB_CW5_BASE (0x65000000)
77 #define DMUB_CW6_BASE (0x66000000)
79 #define DMUB_REGION5_BASE (0xA0000000)
98 for (pos = 0; pos < end; pos += sizeof(buf)) in dmub_flush_buffer_mem()
140 for (i = 0; i < 16; ++i) { in dmub_get_fw_meta_info()
322 dmub_memset(dmub, 0, sizeof(*dmub)); in dmub_srv_create()
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c31 #define AR5008_11NA_OFDM_SHIFT 0
55 {0x000098b0, 0x1e5795e5},
56 {0x000098e0, 0x02008020},
61 {0x000098b0, 0x02108421},
62 {0x000098ec, 0x00000008},
67 {0x000098b0, 0x0e73ff17},
68 {0x000098e0, 0x00000420},
73 {0x000098f0, 0x01400018, 0x01c00018},
78 {0x0000989c, 0x00000500},
79 {0x0000989c, 0x00000800},
[all …]
/openbmc/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]

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