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Searched +full:0 +full:x5c000 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/clk/
H A Dclk_11_5_0_offset.h26 // base address: 0x5c000
27 …CLK1_0_CLK1_CLK_PLL_REQ 0x0410
28 …ne mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0
29 …CLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a
30 …ne mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0
31 …CLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454
32 …ne mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0
33 …CLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e
34 …ne mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
35 …CLK1_0_CLK1_CLK3_DS_CNTL 0x0461
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3588-cru.yaml68 reg = <0xfd7c0000 0x5c000>;
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-mvebu-comphy.txt21 * Lane 0 (USB3/GbE)
26 - #size-cells: should be 0.
47 reg = <0x120000 0x6000>;
53 #size-cells = <0>;
55 CP11X_LABEL(comphy0): phy@0 {
56 reg = <0>;
68 reg = <0x18300 0x300>,
69 <0x1F000 0x400>,
70 <0x5C000 0x400>,
71 <0xe0178 0x8>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0012-Platform-CS1000-Increase-BL2-partition-size.patch30 - RAM_MPU_REGION_BLOCK_1_SIZE=0x4000
34 + # S_DATA_START % RAM_MPU_REGION_BLOCK_1_SIZE = 0
35 + # (S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE) % RAM_MPU_REGION_BLOCK_2_SIZE = 0
36 + RAM_MPU_REGION_BLOCK_1_SIZE=0x10000
37 RAM_MPU_REGION_BLOCK_2_SIZE=0x20000
95 -#define SE_BL2_PARTITION_SIZE (0x18000) /* 96 KB */
96 +#define SE_BL2_PARTITION_SIZE (0x24000) /* 144 KB */
97 #define SE_BL2_BANK_0_OFFSET (0x9000) /* 72nd LBA */
98 #define SE_BL2_BANK_1_OFFSET (0x1002000) /* 32784th LBA */
103 #define BANK_PARTITION_SIZE (0xFE0000) /* 15.875 MB */
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
40 .mr3 = 0,
42 .tpr0 = 0x2ab83def,
43 .tpr1 = 0x18082356,
44 .tpr2 = 0x00034156,
45 .tpr3 = 0x448c5533,
46 .tpr4 = 0x08010d00,
47 .tpr5 = 0x0340b20f,
48 .tpr6 = 0x20d118cc,
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_fw.h14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588s.dtsi23 #size-cells = <0>;
58 cpu_l0: cpu@0 {
61 reg = <0x0>;
82 reg = <0x100>;
101 reg = <0x200>;
120 reg = <0x300>;
139 reg = <0x400>;
160 reg = <0x500>;
179 reg = <0x600>;
200 reg = <0x700>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8953.c40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
[all …]
H A Dgcc-sa8775p.c76 .offset = 0x0,
79 .enable_reg = 0x4b028,
80 .enable_mask = BIT(0),
91 { 0x1, 2 },
96 .offset = 0x0,
113 .offset = 0x1000,
116 .enable_reg = 0x4b028,
128 .offset = 0x4000,
131 .enable_reg = 0x4b028,
143 .offset = 0x5000,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192f.c34 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
35 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
36 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
37 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
38 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
39 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
40 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
41 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
42 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
43 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "MMID", 89, 0 },
36 { "DDR", 104, 0 },
37 { "176", 176, 0 },
38 { "208", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]