xref: /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h (revision a5b2c10c)

/*
 * Copyright (C) 2020  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _clk_11_5_0_OFFSET_HEADER
#define _clk_11_5_0_OFFSET_HEADER


// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5c000
#define mmCLK1_0_CLK1_CLK_PLL_REQ                                                                      0x0410
#define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX                                                             0
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL                                                                 0x044a
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL                                                                 0x0454
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL                                                                 0x045e
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK3_DS_CNTL                                                                     0x0461
#define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX                                                            0
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS                                                                    0x0462
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX                                                           0
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL                                                                 0x0468
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT                                                                 0x04a7
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT                                                                 0x04a8
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT                                                                 0x04a9
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT                                                                 0x04aa
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX                                                        0

#endif