/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | gaudi2_blocks_linux_driver.h | 16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull 17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull 20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull 23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000 25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | faraday,ftpci100.yaml | 18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday 19 Technology) and product ID 0x4321. 34 interrupt-map-mask = <0xf800 0 0 7>; 36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 37 <0x4800 0 0 2 &pci_intc 1>, 38 <0x4800 0 0 3 &pci_intc 2>, 39 <0x4800 0 0 4 &pci_intc 3>, 40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 41 <0x5000 0 0 2 &pci_intc 2>, 42 <0x5000 0 0 3 &pci_intc 3>, [all …]
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H A D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size. 38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; 42 bus-range = <0x00 0xff>; 43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */ 44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */ 45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ 46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ 47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ 48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ 49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ [all …]
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | kuroboxHG.dts | 37 #size-cells = <0>; 41 reg = <0x0>; 44 bus-frequency = <0>; /* Fixed by bootloader */ 46 i-cache-size = <0x4000>; 47 d-cache-size = <0x4000>; 53 reg = <0x0 0x8000000>; 61 store-gathering = <0>; /* 0 == off, !0 == on */ 62 reg = <0x80000000 0x100000>; 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */ [all …]
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H A D | kuroboxHD.dts | 37 #size-cells = <0>; 41 reg = <0x0>; 44 bus-frequency = <0>; /* Fixed by bootloader */ 46 i-cache-size = <0x4000>; 47 d-cache-size = <0x4000>; 53 reg = <0x0 0x4000000>; 61 store-gathering = <0>; /* 0 == off, !0 == on */ 62 reg = <0x80000000 0x100000>; 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */ [all …]
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H A D | mvme5100.dts | 26 #size-cells = <0>; 30 reg = <0x0>; 44 reg = <0x0 0x20000000>; 51 ranges = <0x0 0xfef80000 0x10000>; 52 reg = <0xfef80000 0x10000>; 57 reg = <0x8000 0x80>; 68 reg = <0x8200 0x80>; 78 #address-cells = <0>; 82 reg = <0xf3f80000 0x40000>; 92 reg = <0xfec00000 0x400000>; [all …]
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H A D | tqm8540.dts | 29 #size-cells = <0>; 31 PowerPC,8540@0 { 33 reg = <0>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 47 reg = <0x00000000 0x10000000>; 54 ranges = <0x0 0xe0000000 0x100000>; 55 bus-frequency = <0>; 58 ecm-law@0 { [all …]
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H A D | tqm8541.dts | 28 #size-cells = <0>; 30 PowerPC,8541@0 { 32 reg = <0>; 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 46 reg = <0x00000000 0x10000000>; 53 ranges = <0x0 0xe0000000 0x100000>; 54 bus-frequency = <0>; 57 ecm-law@0 { [all …]
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H A D | tqm8555.dts | 28 #size-cells = <0>; 30 PowerPC,8555@0 { 32 reg = <0>; 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 46 reg = <0x00000000 0x10000000>; 53 ranges = <0x0 0xe0000000 0x100000>; 54 bus-frequency = <0>; 57 ecm-law@0 { [all …]
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H A D | tqm8560.dts | 30 #size-cells = <0>; 32 PowerPC,8560@0 { 34 reg = <0>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 48 reg = <0x00000000 0x10000000>; 55 ranges = <0x0 0xe0000000 0x100000>; 56 bus-frequency = <0>; 59 ecm-law@0 { [all …]
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H A D | tqm8548.dts | 31 #size-cells = <0>; 33 PowerPC,8548@0 { 35 reg = <0>; 38 d-cache-size = <0x8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K 46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 53 ranges = <0x0 0xe0000000 0x100000>; 54 bus-frequency = <0>; 57 ecm-law@0 { 59 reg = <0x0 0x1000>; [all …]
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H A D | tqm8548-bigflash.dts | 31 #size-cells = <0>; 33 PowerPC,8548@0 { 35 reg = <0>; 38 d-cache-size = <0x8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K 46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 53 ranges = <0x0 0xa0000000 0x100000>; 54 bus-frequency = <0>; 57 ecm-law@0 { 59 reg = <0x0 0x1000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/intel/ixp/ |
H A D | intel-ixp42x-goramo-multilink.dts | 25 memory@0 { 31 reg = <0x00000000 0x4000000>; 53 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 68 flash@0,0 { 74 reg = <0 0x00000000 0x1000000>; 78 /* Eraseblock at 0x0fe0000 */ 79 fis-index-block = <0x7f>; 93 interrupt-map-mask = <0xf800 0 0 7>; 96 <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ 97 <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ [all …]
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/openbmc/phosphor-logging/test/openpower-pels/ |
H A D | json_utils_test.cpp | 42 EXPECT_EQ(getNumberString("0x%X", number), "0x7B"); in TEST() 70 EXPECT_EQ(getComponentName(0x1000, 'O'), "some comp"); in TEST() 71 EXPECT_EQ(getComponentName(0x2222, 'O'), "another comp"); in TEST() 72 EXPECT_EQ(getComponentName(0x0001, 'O'), "0x0001"); in TEST() 75 EXPECT_EQ(getComponentName(0x3456, 'B'), "0x3456"); in TEST() 78 EXPECT_EQ(getComponentName(0x4552, 'H'), "ER"); in TEST() 79 EXPECT_EQ(getComponentName(0x584D, 'H'), "XM"); in TEST() 80 EXPECT_EQ(getComponentName(0x5800, 'H'), "0x5800"); in TEST() 81 EXPECT_EQ(getComponentName(0x0058, 'H'), "0x0058"); in TEST()
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | integratorap.dts | 17 #size-cells = <0>; 19 cpu@0 { 28 reg = <0>; 37 operating-points = <71000 0 38 66000 0 39 60000 0 40 48000 0 41 36000 0 42 24000 0 43 12000 0>; [all …]
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/openbmc/linux/drivers/bus/ |
H A D | omap_l3_smx.h | 14 #define L3_COMPONENT 0x000 15 #define L3_CORE 0x018 16 #define L3_AGENT_CONTROL 0x020 17 #define L3_AGENT_STATUS 0x028 18 #define L3_ERROR_LOG 0x058 23 #define L3_ERROR_LOG_ADDR 0x060 26 #define L3_SI_CONTROL 0x020 27 #define L3_SI_FLAG_STATUS_0 0x510 31 #define L3_STATUS_0_MPUIA_BRST (shift << 0) 95 #define L3_SI_FLAG_STATUS_1 0x530 [all …]
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/openbmc/linux/arch/arm/boot/dts/gemini/ |
H A D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>; 31 reg = <0x40000000 0x1000>; 39 offset = <0x0c>; 41 mask = <0xC0000000>; 49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, 159 reg = <0x41000000 0x1000>; 168 reg = <0x42000000 0x100>; 173 pinctrl-0 = <&uart_default_pins>; 179 reg = <0x43000000 0x1000>; 193 reg = <0x45000000 0x100>; [all …]
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/openbmc/qemu/tests/qemu-iotests/ |
H A D | 077 | 25 seq=`basename $0` 34 trap "_cleanup; exit \$status" 0 1 2 3 15 57 aio_write -P 10 0x200 0x200 62 off=0x1000 66 aio_write -P 10 $((off + 0x200)) 0x200 68 aio_write -P 11 $((off + 0x400)) 0x200 73 off=$((off + 0x1000)) 79 aio_write -P 10 0x5000 0x200 81 aio_write -P 11 0x5200 0x200 82 aio_write -P 12 0x5400 0x200 [all …]
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/openbmc/u-boot/board/renesas/gose/ |
H A D | gose_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 44 u32 r0 = 0; in spl_init_sys() 46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys() 56 "orr %0, #0x1800 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/koelsch/ |
H A D | koelsch_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait() 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait() 48 u32 r0 = 0; in spl_init_sys() 50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/porter/ |
H A D | porter_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait() 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait() 48 u32 r0 = 0; in spl_init_sys() 50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
H A D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), 9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), 10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), 11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), 12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), 13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), 14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), 15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), 16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), 17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), [all …]
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/openbmc/linux/arch/mips/boot/dts/loongson/ |
H A D | loongson64-2k1000.dtsi | 15 #size-cells = <0>; 17 cpu0: cpu@0 { 20 reg = <0x0>; 27 #clock-cells = <0>; 33 #address-cells = <0>; 43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */ 44 0 0x40000000 0 0x40000000 0 0x40000000 45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; 51 ranges = <1 0x0 0x0 0x18000000 0x4000>; 56 reg = <0 0x1fe07000 0 0x422>; [all …]
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/openbmc/u-boot/board/intel/cherryhill/ |
H A D | cherryhill.c | 11 GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0, 12 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST), 15 GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0, 16 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR), 22 NA, 29, NA, 0x4c38, NORTH), 25 NA, 27, NA, 0x4c28, NORTH), 28 NA, 20, NA, 0x4858, NORTH), 31 NA, 37, NA, 0x5018, NORTH), 34 NA, 42, NA, 0x5040, NORTH), 37 NA, 35, NA, 0x5008, NORTH), [all …]
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/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
H A D | gaudi_blocks.h | 16 #define mmNIC0_PHY0_BASE 0x0ull 17 #define NIC0_PHY0_MAX_OFFSET 0x9F13 18 #define mmMME0_ACC_BASE 0x7FFC020000ull 19 #define MME0_ACC_MAX_OFFSET 0x5C00 20 #define MME0_ACC_SECTION 0x20000 21 #define mmMME0_SBAB_BASE 0x7FFC040000ull 22 #define MME0_SBAB_MAX_OFFSET 0x5800 23 #define MME0_SBAB_SECTION 0x1000 24 #define mmMME0_PRTN_BASE 0x7FFC041000ull 25 #define MME0_PRTN_MAX_OFFSET 0x5000 [all …]
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