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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damlogic,gxl-mdio-mux.yaml46 reg = <0x558 0xc>;
48 #size-cells = <0>;
53 external_mdio: mdio@0 {
54 reg = <0x0>;
56 #size-cells = <0>;
60 reg = <0x1>;
62 #size-cells = <0>;
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/openbmc/linux/drivers/clk/renesas/
H A Dr9a07g044-cpg.c70 {0, 1},
74 {0, 0},
78 {0, 1},
83 {0, 0},
87 {0, 16},
91 {0, 0},
104 struct cpg_core_clk drp[0];
114 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
187 struct rzg2l_mod_clk drp[0];
192 0x514, 0),
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsystem_manager_gen5.h18 u32 siliconid1; /* 0x00 */
21 u32 wddbg; /* 0x10 */
26 u32 fpgaintfgrp_gbl; /* 0x20 */
31 u32 scanmgrgrp_ctrl; /* 0x30 */
34 u32 frzctrl_vioctrl; /* 0x40 */
36 u32 frzctrl_hioctrl; /* 0x50 */
41 u32 emacgrp_ctrl; /* 0x60 */
45 u32 dmagrp_ctrl; /* 0x70 */
49 u32 iswgrp_handoff[8]; /* 0x80 */
50 u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
20 str r1, [r0, #0x530]
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Diomux-mx51.h47 MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
48 MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
49 MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
50 MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
51 MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
52 MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
53 MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
54 MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
55 MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
56 MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dw83627ehf.rst141 0 (stop) to 255 (full)
146 * 1 Manual mode, write to pwm file any value 0-255 (full speed)
166 * 0 DC output (0 - 12v)
176 (range 0 - 127000)
178 tolerance, unit millidegree Celsius (range 0 - 15000)
216 0x49 only on DHG, selects temperature source for AUX fan,
218 0x4a not completely documented for the EHF and the DHG
224 0x58 Chip ID: 0xa1=EHF 0xc1=DHG
225 0x5e only on DHG, has bits to enable "current mode"
228 0x45b only on EHF, bit 3, vin4 alarm (EHF supports 10
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2600.h17 u32 hwstrap; /* 0x500 */
18 u32 hwstrap_clr; /* 0x504 */
19 u32 hwstrap_protect; /* 0x508 */
23 u32 protection_key; /* 0x000 */
24 u32 chip_id0; /* 0x004 */
25 u32 reserve_0x08; /* 0x008 */
26 u32 reserve_0x0C; /* 0x00C */
27 u32 reserve_0x10; /* 0x010 */
28 u32 chip_id1; /* 0x014 */
29 u32 reserve_0x18; /* 0x018 */
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h19 #define PBCQ_NEST_IRSN_COMPARE 0x1a
20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
21 #define PBCQ_NEST_IRSN_MASK 0x1b
22 #define PBCQ_NEST_LSI_SRC_ID 0x1f
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
24 #define PBCQ_NEST_REGS_COUNT 0x46
25 #define PBCQ_NEST_MMIO_BAR0 0x40
26 #define PBCQ_NEST_MMIO_BAR1 0x41
27 #define PBCQ_NEST_PHB_BAR 0x42
28 #define PBCQ_NEST_MMIO_MASK0 0x43
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dpm-imx5.c26 #define MXC_CCM_CLPCR 0x54
27 #define MXC_CCM_CLPCR_LPM_OFFSET 0
28 #define MXC_CCM_CLPCR_LPM_MASK 0x3
30 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
31 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
33 #define MXC_CORTEXA8_PLAT_LPC 0xc
34 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
37 #define MXC_SRPG_NEON_SRPGCR 0x280
38 #define MXC_SRPG_ARM_SRPGCR 0x2a0
39 #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
[all …]
/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.h49 #define DMACTRL_WOP (1 << 0)
51 #define IEVENT_PERR (1 << 0)
94 #define MACCFG1_TX_EN (1 << 0)
100 #define MIIMCOM_READ (1 << 0)
103 #define RCTRL_PRSDEP_MASK (0x3)
109 #define TSEC_ID (0x000 / 4)
110 #define TSEC_ID2 (0x004 / 4)
111 #define IEVENT (0x010 / 4)
112 #define IMASK (0x014 / 4)
113 #define EDIS (0x018 / 4)
[all …]
/openbmc/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclk_rst.h13 /* pll_out[0] is output A control, pll_out[1] is output B control */
55 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
58 uint crc_reserved0; /* reserved_0, 0x1C */
59 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
60 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
61 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
62 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
63 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
64 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
65 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]

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