Lines Matching +full:0 +full:x558
19 #define PBCQ_NEST_IRSN_COMPARE 0x1a
20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
21 #define PBCQ_NEST_IRSN_MASK 0x1b
22 #define PBCQ_NEST_LSI_SRC_ID 0x1f
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
24 #define PBCQ_NEST_REGS_COUNT 0x46
25 #define PBCQ_NEST_MMIO_BAR0 0x40
26 #define PBCQ_NEST_MMIO_BAR1 0x41
27 #define PBCQ_NEST_PHB_BAR 0x42
28 #define PBCQ_NEST_MMIO_MASK0 0x43
29 #define PBCQ_NEST_MMIO_MASK1 0x44
30 #define PBCQ_NEST_BAR_EN 0x45
31 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
37 #define PBCQ_PCI_REGS_COUNT 0x15
38 #define PBCQ_PCI_BAR2 0x0b
40 #define PBCQ_SPCI_REGS_COUNT 0x5
41 #define PBCQ_SPCI_ASB_ADDR 0x0
42 #define PBCQ_SPCI_ASB_STATUS 0x1
43 #define PBCQ_SPCI_ASB_DATA 0x2
44 #define PBCQ_SPCI_AIB_CAPP_EN 0x3
45 #define PBCQ_SPCI_CAPP_SEC_TMR 0x4
52 #define PHB_LSI_SOURCE_ID 0x100
54 #define PHB_DMA_CHAN_STATUS 0x110
58 #define PHB_CPU_LOADSTORE_STATUS 0x120
62 #define PHB_DMA_MSI_NODE_ID 0x128
63 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
65 #define PHB_CONFIG_DATA 0x130
66 #define PHB_LOCK0 0x138
67 #define PHB_CONFIG_ADDRESS 0x140
68 #define PHB_CA_ENABLE PPC_BIT(0)
74 #define PHB_LOCK1 0x148
75 #define PHB_IVT_BAR 0x150
76 #define PHB_IVT_BAR_ENABLE PPC_BIT(0)
79 #define PHB_RBA_BAR 0x158
80 #define PHB_RBA_BAR_ENABLE PPC_BIT(0)
82 #define PHB_PHB3_CONFIG 0x160
87 #define PHB_RTT_BAR 0x168
88 #define PHB_RTT_BAR_ENABLE PPC_BIT(0)
90 #define PHB_PELTV_BAR 0x188
91 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
93 #define PHB_M32_BASE_ADDR 0x190
94 #define PHB_M32_BASE_MASK 0x198
95 #define PHB_M32_START_ADDR 0x1a0
96 #define PHB_PEST_BAR 0x1a8
97 #define PHB_PEST_BAR_ENABLE PPC_BIT(0)
99 #define PHB_M64_UPPER_BITS 0x1f0
100 #define PHB_INTREP_TIMER 0x1f8
101 #define PHB_DMARD_SYNC 0x200
102 #define PHB_DMARD_SYNC_START PPC_BIT(0)
104 #define PHB_RTC_INVALIDATE 0x208
105 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
107 #define PHB_TCE_KILL 0x210
108 #define PHB_TCE_KILL_ALL PPC_BIT(0)
109 #define PHB_TCE_SPEC_CTL 0x218
110 #define PHB_IODA_ADDR 0x220
111 #define PHB_IODA_AD_AUTOINC PPC_BIT(0)
114 #define PHB_IODA_DATA0 0x228
115 #define PHB_FFI_REQUEST 0x238
118 #define PHB_FFI_LOCK 0x240
119 #define PHB_FFI_LOCK_STATE PPC_BIT(0)
120 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */
121 #define PHB_PHB3_GEN_CAP 0x250
122 #define PHB_PHB3_TCE_CAP 0x258
123 #define PHB_PHB3_IRQ_CAP 0x260
124 #define PHB_PHB3_EEH_CAP 0x268
125 #define PHB_IVC_INVALIDATE 0x2a0
126 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0)
128 #define PHB_IVC_UPDATE 0x2a8
129 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0)
142 #define PHB_PAPR_ERR_INJ_CTL 0x2b0
143 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
150 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8
152 #define PHB_PAPR_ERR_INJ_MASK 0x2c0
155 #define PHB_ETU_ERR_SUMMARY 0x2c8
158 #define UTL_SYS_BUS_CONTROL 0x400
159 #define UTL_STATUS 0x408
160 #define UTL_SYS_BUS_AGENT_STATUS 0x410
161 #define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418
162 #define UTL_SYS_BUS_AGENT_IRQ_EN 0x420
163 #define UTL_SYS_BUS_BURST_SZ_CONF 0x440
164 #define UTL_REVISION_ID 0x448
165 #define UTL_BCLK_DOMAIN_DBG1 0x460
166 #define UTL_BCLK_DOMAIN_DBG2 0x468
167 #define UTL_BCLK_DOMAIN_DBG3 0x470
168 #define UTL_BCLK_DOMAIN_DBG4 0x478
169 #define UTL_BCLK_DOMAIN_DBG5 0x480
170 #define UTL_BCLK_DOMAIN_DBG6 0x488
171 #define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
172 #define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
173 #define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
174 #define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
175 #define UTL_OUT_NP_BUF_ALLOC 0x500
176 #define UTL_IN_NP_BUF_ALLOC 0x510
177 #define UTL_PCIE_TAGS_ALLOC 0x520
178 #define UTL_GBIF_READ_TAGS_ALLOC 0x530
179 #define UTL_PCIE_PORT_CONTROL 0x540
180 #define UTL_PCIE_PORT_STATUS 0x548
181 #define UTL_PCIE_PORT_ERROR_SEV 0x550
182 #define UTL_PCIE_PORT_IRQ_EN 0x558
183 #define UTL_RC_STATUS 0x560
184 #define UTL_RC_ERR_SEVERITY 0x568
185 #define UTL_RC_IRQ_EN 0x570
186 #define UTL_EP_STATUS 0x578
187 #define UTL_EP_ERR_SEVERITY 0x580
188 #define UTL_EP_ERR_IRQ_EN 0x588
189 #define UTL_PCI_PM_CTRL1 0x590
190 #define UTL_PCI_PM_CTRL2 0x598
191 #define UTL_GP_CTL1 0x5a0
192 #define UTL_GP_CTL2 0x5a8
193 #define UTL_PCLK_DOMAIN_DBG1 0x5b0
194 #define UTL_PCLK_DOMAIN_DBG2 0x5b8
195 #define UTL_PCLK_DOMAIN_DBG3 0x5c0
196 #define UTL_PCLK_DOMAIN_DBG4 0x5c8
199 #define PHB_PCIE_SYSTEM_CONFIG 0x600
200 #define PHB_PCIE_BUS_NUMBER 0x608
201 #define PHB_PCIE_SYSTEM_TEST 0x618
202 #define PHB_PCIE_LINK_MANAGEMENT 0x630
204 #define PHB_PCIE_DLP_TRAIN_CTL 0x640
211 #define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648
212 #define PHB_PCIE_SYS_LINK_INIT 0x668
213 #define PHB_PCIE_UTL_CONFIG 0x670
214 #define PHB_PCIE_DLP_CONTROL 0x678
215 #define PHB_PCIE_UTL_ERRLOG1 0x680
216 #define PHB_PCIE_UTL_ERRLOG2 0x688
217 #define PHB_PCIE_UTL_ERRLOG3 0x690
218 #define PHB_PCIE_UTL_ERRLOG4 0x698
219 #define PHB_PCIE_DLP_ERRLOG1 0x6a0
220 #define PHB_PCIE_DLP_ERRLOG2 0x6a8
221 #define PHB_PCIE_DLP_ERR_STATUS 0x6b0
222 #define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8
223 #define PHB_PCIE_UTL_ERR_INJECT 0x6c0
224 #define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8
225 #define PHB_PCIE_LANE_EQ_CNTL0 0x6d0
226 #define PHB_PCIE_LANE_EQ_CNTL1 0x6d8
227 #define PHB_PCIE_LANE_EQ_CNTL2 0x6e0
228 #define PHB_PCIE_LANE_EQ_CNTL3 0x6e8
229 #define PHB_PCIE_STRAPPING 0x700
232 #define PHB_VERSION 0x800
233 #define PHB_RESET 0x808
234 #define PHB_CONTROL 0x810
236 #define PHB_AIB_RX_CRED_INIT_TIMER 0x818
237 #define PHB_AIB_RX_CMD_CRED 0x820
238 #define PHB_AIB_RX_DATA_CRED 0x828
239 #define PHB_AIB_TX_CMD_CRED 0x830
240 #define PHB_AIB_TX_DATA_CRED 0x838
241 #define PHB_AIB_TX_CHAN_MAPPING 0x840
242 #define PHB_AIB_TAG_ENABLE 0x858
243 #define PHB_AIB_FENCE_CTRL 0x860
244 #define PHB_TCE_TAG_ENABLE 0x868
245 #define PHB_TCE_WATERMARK 0x870
246 #define PHB_TIMEOUT_CTRL1 0x878
247 #define PHB_TIMEOUT_CTRL2 0x880
248 #define PHB_Q_DMA_R 0x888
249 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0)
254 #define PHB_AIB_TAG_STATUS 0x900
255 #define PHB_TCE_TAG_STATUS 0x908
258 #define PHB_LEM_FIR_ACCUM 0xc00
259 #define PHB_LEM_FIR_AND_MASK 0xc08
260 #define PHB_LEM_FIR_OR_MASK 0xc10
261 #define PHB_LEM_ERROR_MASK 0xc18
262 #define PHB_LEM_ERROR_AND_MASK 0xc20
263 #define PHB_LEM_ERROR_OR_MASK 0xc28
264 #define PHB_LEM_ACTION0 0xc30
265 #define PHB_LEM_ACTION1 0xc38
266 #define PHB_LEM_WOF 0xc40
267 #define PHB_ERR_STATUS 0xc80
268 #define PHB_ERR1_STATUS 0xc88
269 #define PHB_ERR_INJECT 0xc90
270 #define PHB_ERR_LEM_ENABLE 0xc98
271 #define PHB_ERR_IRQ_ENABLE 0xca0
272 #define PHB_ERR_FREEZE_ENABLE 0xca8
273 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0
274 #define PHB_ERR_LOG_0 0xcc0
275 #define PHB_ERR_LOG_1 0xcc8
276 #define PHB_ERR_STATUS_MASK 0xcd0
277 #define PHB_ERR1_STATUS_MASK 0xcd8
279 #define PHB_OUT_ERR_STATUS 0xd00
280 #define PHB_OUT_ERR1_STATUS 0xd08
281 #define PHB_OUT_ERR_INJECT 0xd10
282 #define PHB_OUT_ERR_LEM_ENABLE 0xd18
283 #define PHB_OUT_ERR_IRQ_ENABLE 0xd20
284 #define PHB_OUT_ERR_FREEZE_ENABLE 0xd28
285 #define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30
286 #define PHB_OUT_ERR_LOG_0 0xd40
287 #define PHB_OUT_ERR_LOG_1 0xd48
288 #define PHB_OUT_ERR_STATUS_MASK 0xd50
289 #define PHB_OUT_ERR1_STATUS_MASK 0xd58
291 #define PHB_INA_ERR_STATUS 0xd80
292 #define PHB_INA_ERR1_STATUS 0xd88
293 #define PHB_INA_ERR_INJECT 0xd90
294 #define PHB_INA_ERR_LEM_ENABLE 0xd98
295 #define PHB_INA_ERR_IRQ_ENABLE 0xda0
296 #define PHB_INA_ERR_FREEZE_ENABLE 0xda8
297 #define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0
298 #define PHB_INA_ERR_LOG_0 0xdc0
299 #define PHB_INA_ERR_LOG_1 0xdc8
300 #define PHB_INA_ERR_STATUS_MASK 0xdd0
301 #define PHB_INA_ERR1_STATUS_MASK 0xdd8
303 #define PHB_INB_ERR_STATUS 0xe00
304 #define PHB_INB_ERR1_STATUS 0xe08
305 #define PHB_INB_ERR_INJECT 0xe10
306 #define PHB_INB_ERR_LEM_ENABLE 0xe18
307 #define PHB_INB_ERR_IRQ_ENABLE 0xe20
308 #define PHB_INB_ERR_FREEZE_ENABLE 0xe28
309 #define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30
310 #define PHB_INB_ERR_LOG_0 0xe40
311 #define PHB_INB_ERR_LOG_1 0xe48
312 #define PHB_INB_ERR_STATUS_MASK 0xe50
313 #define PHB_INB_ERR1_STATUS_MASK 0xe58
316 #define PHB_TRACE_CONTROL 0xf80
317 #define PHB_PERFMON_CONFIG 0xf88
318 #define PHB_PERFMON_CTR0 0xf90
319 #define PHB_PERFMON_CTR1 0xf98
320 #define PHB_PERFMON_CTR2 0xfa0
321 #define PHB_PERFMON_CTR3 0xfa8
322 #define PHB_HOTPLUG_OVERRIDE 0xfb0
355 #define IODA2_IVT_SERVER PPC_BITMASK(0, 23)
363 #define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0, 47)
365 #define IODA2_TVE_1_LEVEL 0
374 #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0)
377 #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0)
383 #define IODA2_M64BT_ENABLE PPC_BIT(0)
406 #define PEST_TTYPE_DMA_WRITE 0