16db1b497SLorenzo Bianconi /* SPDX-License-Identifier: ISC */ 26db1b497SLorenzo Bianconi /* Copyright (C) 2023 MediaTek Inc. */ 36db1b497SLorenzo Bianconi 46db1b497SLorenzo Bianconi #ifndef __MT792X_REGS_H 56db1b497SLorenzo Bianconi #define __MT792X_REGS_H 66db1b497SLorenzo Bianconi 76db1b497SLorenzo Bianconi /* MCU WFDMA1 */ 86db1b497SLorenzo Bianconi #define MT_MCU_WFDMA1_BASE 0x3000 96db1b497SLorenzo Bianconi #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 106db1b497SLorenzo Bianconi 116db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108) 126db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 136db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 146db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 156db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 166db1b497SLorenzo Bianconi 176db1b497SLorenzo Bianconi #define MT_PLE_BASE 0x820c0000 186db1b497SLorenzo Bianconi #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 196db1b497SLorenzo Bianconi 206db1b497SLorenzo Bianconi #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0) 216db1b497SLorenzo Bianconi #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4) 226db1b497SLorenzo Bianconi #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8) 236db1b497SLorenzo Bianconi #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec) 246db1b497SLorenzo Bianconi 256db1b497SLorenzo Bianconi #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n)) 266db1b497SLorenzo Bianconi #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 276db1b497SLorenzo Bianconi 286db1b497SLorenzo Bianconi /* TMAC: band 0(0x21000), band 1(0xa1000) */ 296db1b497SLorenzo Bianconi #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 306db1b497SLorenzo Bianconi #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 316db1b497SLorenzo Bianconi 326db1b497SLorenzo Bianconi #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 336db1b497SLorenzo Bianconi #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 346db1b497SLorenzo Bianconi 356db1b497SLorenzo Bianconi #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090) 366db1b497SLorenzo Bianconi #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094) 376db1b497SLorenzo Bianconi #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 386db1b497SLorenzo Bianconi #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 396db1b497SLorenzo Bianconi 406db1b497SLorenzo Bianconi #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4) 416db1b497SLorenzo Bianconi #define MT_IFS_EIFS GENMASK(8, 0) 426db1b497SLorenzo Bianconi #define MT_IFS_RIFS GENMASK(14, 10) 436db1b497SLorenzo Bianconi #define MT_IFS_SIFS GENMASK(22, 16) 446db1b497SLorenzo Bianconi #define MT_IFS_SLOT GENMASK(30, 24) 456db1b497SLorenzo Bianconi 466db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4) 476db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 486db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 496db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 506db1b497SLorenzo Bianconi 516db1b497SLorenzo Bianconi #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c) 526db1b497SLorenzo Bianconi #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0) 536db1b497SLorenzo Bianconi 546db1b497SLorenzo Bianconi #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 556db1b497SLorenzo Bianconi #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 566db1b497SLorenzo Bianconi 576db1b497SLorenzo Bianconi #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 586db1b497SLorenzo Bianconi #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 596db1b497SLorenzo Bianconi #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 606db1b497SLorenzo Bianconi 616db1b497SLorenzo Bianconi /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ 626db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000) 636db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP(_band, ofs) (MT_WTBLOFF_TOP_BASE(_band) + (ofs)) 646db1b497SLorenzo Bianconi 656db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008) 666db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30) 676db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24) 686db1b497SLorenzo Bianconi 696db1b497SLorenzo Bianconi /* LPON: band 0(0x24200), band 1(0xa4200) */ 706db1b497SLorenzo Bianconi #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 716db1b497SLorenzo Bianconi #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 726db1b497SLorenzo Bianconi 736db1b497SLorenzo Bianconi #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080) 746db1b497SLorenzo Bianconi #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084) 756db1b497SLorenzo Bianconi 766db1b497SLorenzo Bianconi #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4) 776db1b497SLorenzo Bianconi #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 786db1b497SLorenzo Bianconi #define MT_LPON_TCR_SW_WRITE BIT(0) 796db1b497SLorenzo Bianconi 806db1b497SLorenzo Bianconi /* ETBF: band 0(0x24000), band 1(0xa4000) */ 816db1b497SLorenzo Bianconi #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 826db1b497SLorenzo Bianconi #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 836db1b497SLorenzo Bianconi 846db1b497SLorenzo Bianconi #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x150) 856db1b497SLorenzo Bianconi #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 866db1b497SLorenzo Bianconi #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 876db1b497SLorenzo Bianconi 886db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x158) 896db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 906db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 916db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 926db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 936db1b497SLorenzo Bianconi 946db1b497SLorenzo Bianconi /* MIB: band 0(0x24800), band 1(0xa4800) */ 956db1b497SLorenzo Bianconi #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 966db1b497SLorenzo Bianconi #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 976db1b497SLorenzo Bianconi 986db1b497SLorenzo Bianconi #define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004) 996db1b497SLorenzo Bianconi #define MT_MIB_TXDUR_EN BIT(8) 1006db1b497SLorenzo Bianconi #define MT_MIB_RXDUR_EN BIT(9) 1016db1b497SLorenzo Bianconi 1026db1b497SLorenzo Bianconi #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698) 1036db1b497SLorenzo Bianconi #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(31, 16) 1046db1b497SLorenzo Bianconi 1056db1b497SLorenzo Bianconi #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x780) 1066db1b497SLorenzo Bianconi 1076db1b497SLorenzo Bianconi #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 1086db1b497SLorenzo Bianconi #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 1096db1b497SLorenzo Bianconi 1106db1b497SLorenzo Bianconi #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x558) 1116db1b497SLorenzo Bianconi #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x564) 1126db1b497SLorenzo Bianconi #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x568) 1136db1b497SLorenzo Bianconi 1146db1b497SLorenzo Bianconi #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 1156db1b497SLorenzo Bianconi #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 1166db1b497SLorenzo Bianconi 1176db1b497SLorenzo Bianconi #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x770) 1186db1b497SLorenzo Bianconi #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x774) 1196db1b497SLorenzo Bianconi #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x55c) 1206db1b497SLorenzo Bianconi 1216db1b497SLorenzo Bianconi #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x7a8) 1226db1b497SLorenzo Bianconi #define MT_MIB_SDR9_IBF_CNT_MASK GENMASK(31, 16) 1236db1b497SLorenzo Bianconi #define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0) 1246db1b497SLorenzo Bianconi 1256db1b497SLorenzo Bianconi #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090) 1266db1b497SLorenzo Bianconi #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 1276db1b497SLorenzo Bianconi 1286db1b497SLorenzo Bianconi #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x054) 1296db1b497SLorenzo Bianconi #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 1306db1b497SLorenzo Bianconi #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x058) 1316db1b497SLorenzo Bianconi #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 1326db1b497SLorenzo Bianconi 1336db1b497SLorenzo Bianconi #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0) 1346db1b497SLorenzo Bianconi #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4) 1356db1b497SLorenzo Bianconi #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc) 1366db1b497SLorenzo Bianconi 1376db1b497SLorenzo Bianconi #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 1386db1b497SLorenzo Bianconi #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 1396db1b497SLorenzo Bianconi 1406db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688) 1416db1b497SLorenzo Bianconi #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 1426db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690) 1436db1b497SLorenzo Bianconi #define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0) 1446db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518) 1456db1b497SLorenzo Bianconi #define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0) 1466db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520) 1476db1b497SLorenzo Bianconi #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0) 1486db1b497SLorenzo Bianconi 1496db1b497SLorenzo Bianconi #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4)) 1506db1b497SLorenzo Bianconi #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0) 1516db1b497SLorenzo Bianconi 1526db1b497SLorenzo Bianconi #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x7dc + ((n) << 2)) 1536db1b497SLorenzo Bianconi #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x7ec + ((n) << 2)) 1546db1b497SLorenzo Bianconi #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 1556db1b497SLorenzo Bianconi #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 1566db1b497SLorenzo Bianconi 1576db1b497SLorenzo Bianconi #define MT_WTBLON_TOP_BASE 0x820d4000 1586db1b497SLorenzo Bianconi #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 1596db1b497SLorenzo Bianconi 1606db1b497SLorenzo Bianconi #define MT_WTBL_UPDATE_BUSY BIT(31) 1616db1b497SLorenzo Bianconi 1626db1b497SLorenzo Bianconi #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0) 1636db1b497SLorenzo Bianconi #define MT_WTBL_ITCR_WR BIT(16) 1646db1b497SLorenzo Bianconi #define MT_WTBL_ITCR_EXEC BIT(31) 1656db1b497SLorenzo Bianconi #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8) 1666db1b497SLorenzo Bianconi #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc) 1676db1b497SLorenzo Bianconi #define MT_WTBL_SPE_IDX_SEL BIT(6) 1686db1b497SLorenzo Bianconi 1696db1b497SLorenzo Bianconi #define MT_WTBL_BASE 0x820d8000 1706db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_ID GENMASK(14, 8) 1716db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_DW GENMASK(7, 2) 1726db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 1736db1b497SLorenzo Bianconi FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 1746db1b497SLorenzo Bianconi FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 1756db1b497SLorenzo Bianconi 1766db1b497SLorenzo Bianconi /* AGG: band 0(0x20800), band 1(0xa0800) */ 1776db1b497SLorenzo Bianconi #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 1786db1b497SLorenzo Bianconi #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 1796db1b497SLorenzo Bianconi 1806db1b497SLorenzo Bianconi #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4) 1816db1b497SLorenzo Bianconi #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4) 1826db1b497SLorenzo Bianconi #define MT_AGG_PCR0_MM_PROT BIT(0) 1836db1b497SLorenzo Bianconi #define MT_AGG_PCR0_GF_PROT BIT(1) 1846db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW20_PROT BIT(2) 1856db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW40_PROT BIT(4) 1866db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW80_PROT BIT(6) 1876db1b497SLorenzo Bianconi #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 1886db1b497SLorenzo Bianconi #define MT_AGG_PCR0_VHT_PROT BIT(13) 1896db1b497SLorenzo Bianconi #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 1906db1b497SLorenzo Bianconi 1916db1b497SLorenzo Bianconi #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 1926db1b497SLorenzo Bianconi #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 1936db1b497SLorenzo Bianconi 1946db1b497SLorenzo Bianconi #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084) 1956db1b497SLorenzo Bianconi #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 1966db1b497SLorenzo Bianconi #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 1976db1b497SLorenzo Bianconi 1986db1b497SLorenzo Bianconi #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098) 1996db1b497SLorenzo Bianconi #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 2006db1b497SLorenzo Bianconi #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 2016db1b497SLorenzo Bianconi #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 2026db1b497SLorenzo Bianconi #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 2036db1b497SLorenzo Bianconi 2046db1b497SLorenzo Bianconi #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0) 2056db1b497SLorenzo Bianconi #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4) 2066db1b497SLorenzo Bianconi 2076db1b497SLorenzo Bianconi /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 2086db1b497SLorenzo Bianconi #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 2096db1b497SLorenzo Bianconi #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 2106db1b497SLorenzo Bianconi 2116db1b497SLorenzo Bianconi #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080) 2126db1b497SLorenzo Bianconi #define MT_ARB_SCR_TX_DISABLE BIT(8) 2136db1b497SLorenzo Bianconi #define MT_ARB_SCR_RX_DISABLE BIT(9) 2146db1b497SLorenzo Bianconi 2156db1b497SLorenzo Bianconi #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4) 2166db1b497SLorenzo Bianconi 2176db1b497SLorenzo Bianconi /* RMAC: band 0(0x21400), band 1(0xa1400) */ 2186db1b497SLorenzo Bianconi #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 2196db1b497SLorenzo Bianconi #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 2206db1b497SLorenzo Bianconi 2216db1b497SLorenzo Bianconi #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 2226db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 2236db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 2246db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_VERSION BIT(3) 2256db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 2266db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_MCAST BIT(5) 2276db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_BCAST BIT(6) 2286db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 2296db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 2306db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 2316db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 2326db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 2336db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 2346db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 2356db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_CTS BIT(14) 2366db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_RTS BIT(15) 2376db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 2386db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 2396db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 2406db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 2416db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_NDPA BIT(20) 2426db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 2436db1b497SLorenzo Bianconi 2446db1b497SLorenzo Bianconi #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 2456db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_ACK BIT(4) 2466db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 2476db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_BA BIT(6) 2486db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_CFEND BIT(7) 2496db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_CFACK BIT(8) 2506db1b497SLorenzo Bianconi 2516db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4) 2526db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 2536db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 2546db1b497SLorenzo Bianconi 2556db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8) 2566db1b497SLorenzo Bianconi #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 2576db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 2586db1b497SLorenzo Bianconi 2596db1b497SLorenzo Bianconi /* WFDMA0 */ 2606db1b497SLorenzo Bianconi #define MT_WFDMA0_BASE 0xd4000 2616db1b497SLorenzo Bianconi #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 2626db1b497SLorenzo Bianconi 2636db1b497SLorenzo Bianconi #define MT_WFDMA0_RST MT_WFDMA0(0x100) 2646db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 2656db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 2666db1b497SLorenzo Bianconi 2676db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 2686db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 2696db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 2706db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 2716db1b497SLorenzo Bianconi 2726db1b497SLorenzo Bianconi #define MT_MCU_CMD MT_WFDMA0(0x1f0) 2736db1b497SLorenzo Bianconi #define MT_MCU_CMD_WAKE_RX_PCIE BIT(0) 2746db1b497SLorenzo Bianconi #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 2756db1b497SLorenzo Bianconi #define MT_MCU_CMD_STOP_DMA BIT(2) 2766db1b497SLorenzo Bianconi #define MT_MCU_CMD_RESET_DONE BIT(3) 2776db1b497SLorenzo Bianconi #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 2786db1b497SLorenzo Bianconi #define MT_MCU_CMD_NORMAL_STATE BIT(5) 2796db1b497SLorenzo Bianconi #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 2806db1b497SLorenzo Bianconi 2816db1b497SLorenzo Bianconi #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4) 2826db1b497SLorenzo Bianconi 2836db1b497SLorenzo Bianconi #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200) 2846db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */ 2856db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS2 BIT(2) /* Rx data */ 2866db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS4 BIT(22) /* Rx mcu after fw downloaded */ 2876db1b497SLorenzo Bianconi #define HOST_TX_DONE_INT_STS16 BIT(26) 2886db1b497SLorenzo Bianconi #define HOST_TX_DONE_INT_STS17 BIT(27) /* MCU tx done*/ 2896db1b497SLorenzo Bianconi 2906db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 2916db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 2926db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1) 2936db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 2946db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3) 2956db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6) 2966db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL BIT(9) 2976db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) 2986db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15) 2996db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 3006db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 3016db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 3026db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30) 3036db1b497SLorenzo Bianconi 304*c9072f11SLorenzo Bianconi #define HOST_RX_DONE_INT_ENA0 BIT(0) 305*c9072f11SLorenzo Bianconi #define HOST_RX_DONE_INT_ENA1 BIT(1) 306*c9072f11SLorenzo Bianconi #define HOST_RX_DONE_INT_ENA2 BIT(2) 307*c9072f11SLorenzo Bianconi #define HOST_RX_DONE_INT_ENA3 BIT(3) 308*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA0 BIT(4) 309*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA1 BIT(5) 310*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA2 BIT(6) 311*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA3 BIT(7) 312*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA4 BIT(8) 313*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA5 BIT(9) 314*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA6 BIT(10) 315*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA7 BIT(11) 316*c9072f11SLorenzo Bianconi #define HOST_RX_COHERENT_EN BIT(20) 317*c9072f11SLorenzo Bianconi #define HOST_TX_COHERENT_EN BIT(21) 318*c9072f11SLorenzo Bianconi #define MCU2HOST_SW_INT_ENA BIT(29) 319*c9072f11SLorenzo Bianconi #define HOST_TX_DONE_INT_ENA18 BIT(30) 320*c9072f11SLorenzo Bianconi 321*c9072f11SLorenzo Bianconi #define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA 322*c9072f11SLorenzo Bianconi 3236db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 3246db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280) 3256db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 3266db1b497SLorenzo Bianconi #define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE BIT(6) 3276db1b497SLorenzo Bianconi #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 3286db1b497SLorenzo Bianconi 3296db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600) 3306db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604) 3316db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608) 3326db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c) 3336db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610) 3346db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614) 3356db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618) 3366db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING15_EXT_CTRL MT_WFDMA0(0x63c) 3376db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640) 3386db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644) 3396db1b497SLorenzo Bianconi 3406db1b497SLorenzo Bianconi #define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0) 3416db1b497SLorenzo Bianconi #define MT_WPDMA0_BASE_PTR_MASK GENMASK(31, 16) 3426db1b497SLorenzo Bianconi 3436db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680) 3446db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684) 3456db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688) 3466db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c) 3476db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690) 3486db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694) 3496db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING6_EXT_CTRL MT_WFDMA0(0x698) 3506db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING7_EXT_CTRL MT_WFDMA0(0x69c) 3516db1b497SLorenzo Bianconi 3526db1b497SLorenzo Bianconi #define MT_TX_RING_BASE MT_WFDMA0(0x300) 3536db1b497SLorenzo Bianconi #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500) 3546db1b497SLorenzo Bianconi 3556db1b497SLorenzo Bianconi /* WFDMA CSR */ 3566db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_BASE 0xd7000 3576db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 3586db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 3596db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 3606db1b497SLorenzo Bianconi 3616db1b497SLorenzo Bianconi #define MT_SWDEF_BASE 0x41f200 3626db1b497SLorenzo Bianconi #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 3636db1b497SLorenzo Bianconi #define MT_SWDEF_MODE MT_SWDEF(0x3c) 3646db1b497SLorenzo Bianconi #define MT_SWDEF_NORMAL_MODE 0 3656db1b497SLorenzo Bianconi #define MT_SWDEF_ICAP_MODE 1 3666db1b497SLorenzo Bianconi #define MT_SWDEF_SPECTRUM_MODE 2 3676db1b497SLorenzo Bianconi 3686db1b497SLorenzo Bianconi #define MT_TOP_BASE 0x18060000 3696db1b497SLorenzo Bianconi #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 3706db1b497SLorenzo Bianconi 3716db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10) 3726db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 3736db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 3746db1b497SLorenzo Bianconi 3756db1b497SLorenzo Bianconi #define MT_TOP_MISC MT_TOP(0xf0) 3766db1b497SLorenzo Bianconi #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 3776db1b497SLorenzo Bianconi 3786db1b497SLorenzo Bianconi #define MT_MCU_WPDMA0_BASE 0x54000000 3796db1b497SLorenzo Bianconi #define MT_MCU_WPDMA0(ofs) (MT_MCU_WPDMA0_BASE + (ofs)) 3806db1b497SLorenzo Bianconi 3816db1b497SLorenzo Bianconi #define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120) 3826db1b497SLorenzo Bianconi #define MT_WFDMA_NEED_REINIT BIT(1) 3836db1b497SLorenzo Bianconi 3846db1b497SLorenzo Bianconi #define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs)) 3856db1b497SLorenzo Bianconi #define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600) 3866db1b497SLorenzo Bianconi #define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0) 3876db1b497SLorenzo Bianconi 3886db1b497SLorenzo Bianconi #define MT_HW_BOUND 0x70010020 3896db1b497SLorenzo Bianconi #define MT_HW_CHIPID 0x70010200 3906db1b497SLorenzo Bianconi #define MT_HW_REV 0x70010204 3916db1b497SLorenzo Bianconi 3926db1b497SLorenzo Bianconi #define MT_PCIE_MAC_BASE 0x10000 3936db1b497SLorenzo Bianconi #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 3946db1b497SLorenzo Bianconi #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 3956db1b497SLorenzo Bianconi #define MT_PCIE_MAC_PM MT_PCIE_MAC(0x194) 3966db1b497SLorenzo Bianconi #define MT_PCIE_MAC_PM_L0S_DIS BIT(8) 3976db1b497SLorenzo Bianconi 3986db1b497SLorenzo Bianconi #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs)) 3996db1b497SLorenzo Bianconi #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004) 4006db1b497SLorenzo Bianconi #define MT_DMASHDL_DMASHDL_BYPASS BIT(28) 4016db1b497SLorenzo Bianconi #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008) 4026db1b497SLorenzo Bianconi #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c) 4036db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_SEQ_ORDER BIT(16) 4046db1b497SLorenzo Bianconi #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010) 4056db1b497SLorenzo Bianconi #define MT_DMASHDL_REFILL_MASK GENMASK(31, 16) 4066db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c) 4076db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0) 4086db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16) 4096db1b497SLorenzo Bianconi 4106db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2)) 4116db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0) 4126db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16) 4136db1b497SLorenzo Bianconi 4146db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2)) 4156db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0) 4166db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8)) 4176db1b497SLorenzo Bianconi 4186db1b497SLorenzo Bianconi #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2)) 4196db1b497SLorenzo Bianconi 4206db1b497SLorenzo Bianconi #define MT_WFDMA_HOST_CONFIG 0x7c027030 4216db1b497SLorenzo Bianconi #define MT_WFDMA_HOST_CONFIG_USB_RXEVT_EP4_EN BIT(6) 4226db1b497SLorenzo Bianconi 4236db1b497SLorenzo Bianconi #define MT_UMAC(ofs) (0x74000000 + (ofs)) 4246db1b497SLorenzo Bianconi #define MT_UDMA_TX_QSEL MT_UMAC(0x008) 4256db1b497SLorenzo Bianconi #define MT_FW_DL_EN BIT(3) 4266db1b497SLorenzo Bianconi 4276db1b497SLorenzo Bianconi #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c) 4286db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0) 4296db1b497SLorenzo Bianconi #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8) 4306db1b497SLorenzo Bianconi 4316db1b497SLorenzo Bianconi #define MT_UDMA_WLCFG_0 MT_UMAC(0x18) 4326db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_TO GENMASK(7, 0) 4336db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_LMT GENMASK(15, 8) 4346db1b497SLorenzo Bianconi #define MT_WL_TX_TMOUT_FUNC_EN BIT(16) 4356db1b497SLorenzo Bianconi #define MT_WL_TX_DPH_CHK_EN BIT(17) 4366db1b497SLorenzo Bianconi #define MT_WL_RX_MPSZ_PAD0 BIT(18) 4376db1b497SLorenzo Bianconi #define MT_WL_RX_FLUSH BIT(19) 4386db1b497SLorenzo Bianconi #define MT_TICK_1US_EN BIT(20) 4396db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_EN BIT(21) 4406db1b497SLorenzo Bianconi #define MT_WL_RX_EN BIT(22) 4416db1b497SLorenzo Bianconi #define MT_WL_TX_EN BIT(23) 4426db1b497SLorenzo Bianconi #define MT_WL_RX_BUSY BIT(30) 4436db1b497SLorenzo Bianconi #define MT_WL_TX_BUSY BIT(31) 4446db1b497SLorenzo Bianconi 4456db1b497SLorenzo Bianconi #define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20) 4466db1b497SLorenzo Bianconi #define MT_UDMA_CONN_WFSYS_INIT_DONE BIT(22) 4476db1b497SLorenzo Bianconi #define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24) 4486db1b497SLorenzo Bianconi 4496db1b497SLorenzo Bianconi #define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs)) 4506db1b497SLorenzo Bianconi #define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090) 4516db1b497SLorenzo Bianconi 4526db1b497SLorenzo Bianconi #define MT_UWFDMA0(ofs) (0x7c024000 + (ofs)) 4536db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208) 4546db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0) 4556db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG_EXT1 MT_UWFDMA0(0x2b4) 4566db1b497SLorenzo Bianconi #define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2)) 4576db1b497SLorenzo Bianconi 4586db1b497SLorenzo Bianconi #define MT_CONN_STATUS 0x7c053c10 4596db1b497SLorenzo Bianconi #define MT_WIFI_PATCH_DL_STATE BIT(0) 4606db1b497SLorenzo Bianconi 4616db1b497SLorenzo Bianconi #define MT_CONN_ON_LPCTL 0x7c060010 4626db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_SET_OWN BIT(0) 4636db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_CLR_OWN BIT(1) 4646db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_OWN_SYNC BIT(2) 4656db1b497SLorenzo Bianconi 4666db1b497SLorenzo Bianconi #define MT_CONN_ON_MISC 0x7c0600f0 4676db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_PWR_ON BIT(0) 4686db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_N9_ON BIT(1) 4696db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0) 4706db1b497SLorenzo Bianconi 4716db1b497SLorenzo Bianconi #define MT_WF_SW_DEF_CR(ofs) (0x401a00 + (ofs)) 4726db1b497SLorenzo Bianconi #define MT_WF_SW_DEF_CR_USB_MCU_EVENT MT_WF_SW_DEF_CR(0x028) 4736db1b497SLorenzo Bianconi #define MT_WF_SW_SER_TRIGGER_SUSPEND BIT(6) 4746db1b497SLorenzo Bianconi #define MT_WF_SW_SER_DONE_SUSPEND BIT(7) 4756db1b497SLorenzo Bianconi 476c693f2f0SLorenzo Bianconi #define WFSYS_SW_RST_B BIT(0) 477c693f2f0SLorenzo Bianconi #define WFSYS_SW_INIT_DONE BIT(4) 478c693f2f0SLorenzo Bianconi 4796db1b497SLorenzo Bianconi #endif /* __MT792X_REGS_H */ 480