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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dcache-uniphier.c17 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */
18 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
19 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
20 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
21 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
22 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
23 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
24 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
27 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */
30 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
[all …]
/openbmc/qemu/hw/tricore/
H A Dtc27x_soc.c32 [TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
33 [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
34 [TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
35 [TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
36 [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
37 [TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
38 [TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
39 [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
40 [TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
41 [TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-sld8.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 <0x506c0000 0x400>;
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-sld8.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/drivers/media/pci/bt8xx/
H A Ddvb-bt8xx.c37 } while (0)
93 if (card->nfeeds == 0) in dvb_bt8xx_stop_feed()
97 return 0; in dvb_bt8xx_stop_feed()
107 return 0; in is_pci_slot_eq()
116 for (card_nr = 0; card_nr < bt878_num; card_nr++) in dvb_bt8xx_878_match()
124 static u8 mt352_clock_config [] = { 0x89, 0x38, 0x38 }; in thomson_dtt7579_demod_init()
125 static u8 mt352_reset [] = { 0x50, 0x80 }; in thomson_dtt7579_demod_init()
126 static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 }; in thomson_dtt7579_demod_init()
127 static u8 mt352_agc_cfg [] = { 0x67, 0x28, 0x20 }; in thomson_dtt7579_demod_init()
128 static u8 mt352_gpp_ctl_cfg [] = { 0x8C, 0x33 }; in thomson_dtt7579_demod_init()
[all …]