Home
last modified time | relevance | path

Searched +full:0 +full:x50020000 (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,stm32-syscon.yaml59 reg = <0x50020000 0x400>;
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmotionpro.dts74 reg = <0x68>;
80 reg = <0x8000 0x4000>;
89 ranges = <0 0 0xff000000 0x01000000
90 1 0 0x50000000 0x00010000
91 2 0 0x50010000 0x00010000
92 3 0 0x50020000 0x00010000>;
95 kollmorgen@1,0 {
97 reg = <1 0 0x10000>;
98 interrupts = <1 1 0>;
102 cpld@2,0 {
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
54 reg = <0xb3000000 0x1000>;
[all …]
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
/openbmc/u-boot/drivers/net/
H A Dbcm-sf2-eth-gmac.h15 #define GMAC0_REG_BASE 0x18042000
17 #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
18 #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
19 #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
22 #define GMAC_DMA_PTR_OFFSET 0x04
23 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
24 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
25 #define GMAC_DMA_STATUS0_OFFSET 0x10
26 #define GMAC_DMA_STATUS1_OFFSET 0x14
28 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
[all …]
H A Dmcfmii.c31 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
32 (REG & 0x1f) << 18))
33 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
34 (REG & 0x1f) << 18) | (VAL & 0xffff))
37 # define CONFIG_SYS_UNSPEC_PHYID 0
40 # define CONFIG_SYS_UNSPEC_STRID 0
57 {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
58 {0x00406322, "BCM5222"}, /* Broadcom 5222 */
59 {0x02a80150, "Intel82555"}, /* Intel 82555 */
60 {0x0016f870, "LSI80225"}, /* LSI 80225 */
[all …]
H A Dmpc8xx_fec.c58 0,
62 0,
72 0,
124 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { in fec_initialize()
129 memset(dev, 0, sizeof(*dev)); in fec_initialize()
133 if (i == 0) in fec_initialize()
164 if (retval < 0) in fec_initialize()
181 j = 0; in fec_send()
197 out_be32(&fecp->fec_x_des_active, 0x01000000); in fec_send()
199 j = 0; in fec_send()
[all …]
/openbmc/linux/drivers/net/ethernet/arc/
H A Demac_mdio.c22 * returns: 0 on success, -ETIMEDOUT on a timeout.
28 for (i = 0; i < ARC_MDIO_COMPLETE_POLL_COUNT * 40; i++) { in arc_mdio_complete_wait()
36 return 0; in arc_mdio_complete_wait()
63 0x60020000 | (phy_addr << 23) | (reg_num << 18)); in arc_mdio_read()
66 if (error < 0) in arc_mdio_read()
69 value = arc_reg_get(priv, R_MDIO) & 0xffff; in arc_mdio_read()
84 * returns: 0 on success, -ETIMEDOUT on a timeout.
98 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); in arc_mdio_write()
116 gpiod_set_value_cansleep(data->reset_gpio, 0); in arc_mdio_reset()
119 return 0; in arc_mdio_reset()
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c47 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
48 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
49 #define mk_mii_end 0
59 BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0); in fs_enet_fec_mii_read()
64 for (i = 0; i < FEC_MII_LOOPS; i++) in fs_enet_fec_mii_read()
65 if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0) in fs_enet_fec_mii_read()
70 ret = in_be32(&fecp->fec_mii_data) & 0xffff; in fs_enet_fec_mii_read()
83 BUG_ON((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0); in fs_enet_fec_mii_write()
88 for (i = 0; i < FEC_MII_LOOPS; i++) in fs_enet_fec_mii_write()
89 if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0) in fs_enet_fec_mii_write()
[all …]
H A Dmac-fcc.c71 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
72 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
73 #define mk_mii_end 0
90 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); in do_pd_setup()
94 fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); in do_pd_setup()
113 return 0; in do_pd_setup()
133 if (do_pd_setup(fep) != 0) in setup_data()
140 return 0; in setup_data()
155 return 0; in allocate_bd()
187 W32(ep, fen_gaddrh, 0); in set_multicast_start()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml54 - description: The field mask of IRQ mux, needed if different of 0xf
61 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
64 '^gpio@[0-9a-f]*$':
114 minimum: 0
118 "^(.+-hog(-[0-9]+)?)$":
130 '-[0-9]*$':
152 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
153 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
155 * 0 : GPIO
156 * 1 : Alternate Function 0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */
17 #define IRAM_SIZE 0x00020000 /* 128 KB */
19 #define LOW_LEVEL_SRAM_STACK 0x1001E000
24 #define AIPS1_BASE_ADDR 0x43F00000
26 #define MAX_BASE_ADDR 0x43F04000
27 #define EVTMON_BASE_ADDR 0x43F08000
28 #define CLKCTL_BASE_ADDR 0x43F0C000
29 #define I2C1_BASE_ADDR 0x43F80000
30 #define I2C3_BASE_ADDR 0x43F84000
31 #define ATA_BASE_ADDR 0x43F8C000
[all …]
/openbmc/linux/Documentation/arch/arm/sa1100/
H A Dassabet.rst91 load zImage -r -b 0x100000
95 load -m ymodem -r -b 0x100000
99 fis create "Linux kernel" -b 0x100000 -l 0xc0000
108 load ramdisk_image.gz -r -b 0x800000
119 exec -b 0x100000 -l 0xc0000
140 load sample_img.jffs2 -r -b 0x100000
144 RedBoot> load sample_img.jffs2 -r -b 0x100000
145 Raw file loaded 0x00100000-0x00377424
154 0x500E0000 .. 0x503C0000
162 size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h12 #define GLOB_CTRL 0x00UL /* Control */
13 #define GLOB_STAT 0x04UL /* Status */
14 #define GLOB_PSIZE 0x08UL /* Packet Size */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
18 #define GLOB_REG_SIZE 0x18UL
20 #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
21 #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
22 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
[all …]
H A Dsunhme.h15 #define GREG_SWRESET 0x000UL /* Software Reset */
16 #define GREG_CFG 0x004UL /* Config Register */
17 #define GREG_STAT 0x100UL /* Status */
18 #define GREG_IMASK 0x104UL /* Interrupt Mask */
19 #define GREG_REG_SIZE 0x108UL
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50.dtsi48 #size-cells = <0>;
49 cpu@0 {
52 reg = <0x0>;
60 reg = <0x0fffc000 0x4000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
79 clock-frequency = <0>;
84 #clock-cells = <0>;
89 usbphy0: usbphy-0 {
[all …]
H A Dimx53.dtsi51 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0>;
84 reg = <0x0fffc000 0x4000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
102 #clock-cells = <0>;
103 clock-frequency = <0>;
108 #clock-cells = <0>;
119 usbphy0: usbphy-0 {
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h27 u32 cgr0; /* Clock Gating Control 0 */
33 u32 dcvr0; /* DPTC Comparator Value 0 */
37 u32 ltr0; /* Load Tracking 0 */
41 u32 ltbr0; /* Load Tracking Buffer 0 */
43 u32 pcmr0; /* Power Management Control 0 */
47 u32 lpimr0; /* Low Power Interrupt Mask 0 */
53 u32 ctl0; /* control 0 */
54 u32 cfg0; /* configuration 0 */
104 u32 res1[0x1f1];
106 u32 fuse_regs[0x20];
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/3com/
H A D3c574_cs.c46 0x0800-0x0fff can translated to the PIO FIFO. Thus memory operations (faster
48 This is enabled by setting the 0x10 bit in the PCMCIA LAN COR.
51 This is configured by setting the 0x20 bit in the PCMCIA LAN COR.
55 configuration space registers. Window 0 is the regular Boomerang/Odie
106 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
112 INT_MODULE_PARM(full_duplex, 0);
127 #define EL3_DATA 0x00
128 #define EL3_CMD 0x0e
129 #define EL3_STATUS 0x0e
136 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
[all …]
H A D3c59x.c26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
222 CH_3C590 = 0,
[all …]
/openbmc/linux/drivers/bus/
H A Dti-sysc.c30 #define DIS_SGX BIT(0)
167 writew_relaxed(value & 0xffff, ddata->module_va + offset); in sysc_write()
170 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_write()
191 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_read()
213 if (offset < 0) in sysc_read_revision()
214 return 0; in sysc_read_revision()
223 if (offset < 0) in sysc_read_sysconfig()
224 return 0; in sysc_read_sysconfig()
233 if (offset < 0) in sysc_read_sysstatus()
234 return 0; in sysc_read_sysstatus()
[all …]