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/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dfaraday,ftgpio010.yaml59 reg = <0x4d000000 0x100>;
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware.h30 #define DM_TIMER0_BASE 0x4802C000
31 #define DM_TIMER1_BASE 0x4802E000
32 #define DM_TIMER2_BASE 0x48040000
33 #define DM_TIMER3_BASE 0x48042000
34 #define DM_TIMER4_BASE 0x48044000
35 #define DM_TIMER5_BASE 0x48046000
36 #define DM_TIMER6_BASE 0x48048000
37 #define DM_TIMER7_BASE 0x4804A000
40 #define GPIO0_BASE 0x48032000
41 #define GPIO1_BASE 0x4804C000
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p-main.dtsi10 reg = <0x00 0x70000000 0x00 0x10000>;
13 ranges = <0x00 0x00 0x70000000 0x10000>;
23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
25 <0x01 0x00000000 0x00 0x2000>, /* GICC */
26 <0x01 0x00010000 0x00 0x1000>, /* GICH */
27 <0x01 0x00020000 0x00 0x2000>; /* GICV */
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
[all …]
H A Dk3-am62a-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x01 0x00000000 0x00 0x2000>, /* GICC */
22 <0x01 0x00010000 0x00 0x1000>, /* GICH */
23 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
46 reg = <0x00 0x00100000 0x00 0x20000>;
[all …]
H A Dk3-am62-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x01 0x00000000 0x00 0x2000>, /* GICC */
27 <0x01 0x00010000 0x00 0x1000>, /* GICH */
28 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
46 reg = <0x00 0x00100000 0x00 0x20000>;
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
49 reg = <0x00000014 0x4>;
[all …]
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c32 #define CPG_PLL1CR 0xE6150028
33 #define CPG_PLL3CR 0xE61500DC
50 if (cpu_type == 0x4A) { in blanche_init_sys()
51 writel(0x4D000000, CPG_PLL1CR); in blanche_init_sys()
52 writel(0x4F000000, CPG_PLL3CR); in blanche_init_sys()
56 writel(0xA5A5A500, &rwdt->rwtcsra); in blanche_init_sys()
57 writel(0xA5A5A500, &swdt->swtcsra); in blanche_init_sys()
63 { 0x0004, 0x0bffffff }, in blanche_init_pfc()
64 { 0x0008, 0x002fffff }, in blanche_init_pfc()
65 { 0x0014, 0x00000fff }, in blanche_init_pfc()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h21 #define EMIF1_BASE 0x4c000000
23 #define EMIF2_BASE 0x4d000000
25 #define EMIF_4D 0x4
26 #define EMIF_4D5 0x5
32 #define EMIF_REG_SCHEME_MASK (0x3 << 30)
34 #define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
36 #define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
38 #define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
39 #define EMIF_REG_MINOR_REVISION_SHIFT 0
40 #define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/openbmc/qemu/disas/
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]