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/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/u-boot/board/atmel/sama5d3_xplained/
H A Dsama5d3_xplained.c58 at91_set_pio_output(AT91_PIO_PORTE, 3, 0); in sama5d3_xplained_usb_hw_init()
59 at91_set_pio_output(AT91_PIO_PORTE, 4, 0); in sama5d3_xplained_usb_hw_init()
66 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ in sama5d3_xplained_mci0_hw_init()
81 return 0; in board_late_init()
91 return 0; in board_early_init_f()
98 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
109 return 0; in board_init()
117 return 0; in dram_init()
149 ddr2->rtr = 0x411; in ddr2_conf()
191 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | in at91_pmc_init()
[all …]
/openbmc/linux/include/linux/soc/pxa/
H A Dcpu.h18 * PXA210 B0 0x69052922 0x2926C013
19 * PXA210 B1 0x69052923 0x3926C013
20 * PXA210 B2 0x69052924 0x4926C013
21 * PXA210 C0 0x69052D25 0x5926C013
23 * PXA250 A0 0x69052100 0x09264013
24 * PXA250 A1 0x69052101 0x19264013
25 * PXA250 B0 0x69052902 0x29264013
26 * PXA250 B1 0x69052903 0x39264013
27 * PXA250 B2 0x69052904 0x49264013
28 * PXA250 C0 0x69052D05 0x59264013
[all …]
/openbmc/u-boot/board/laird/wb50n/
H A Dwb50n.c66 return 0; in board_early_init_f()
72 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
78 return 0; in board_init()
85 return 0; in dram_init()
92 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); in board_phy_config()
95 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); in board_phy_config()
98 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); in board_phy_config()
100 return 0; in board_phy_config()
105 int rc = 0; in board_eth_init()
107 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); in board_eth_init()
[all …]
/openbmc/u-boot/board/laird/wb45n/
H A Dwb45n.c36 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | in wb45n_nand_hw_init()
37 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), in wb45n_nand_hw_init()
58 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ in wb45n_nand_hw_init()
68 at91_set_gpio_output(AT91_PIN_PA28, 0); in wb45n_gpio_hw_init()
71 at91_set_gpio_input(AT91_PIN_PB11, 0); in wb45n_gpio_hw_init()
72 at91_set_gpio_output(AT91_PIN_PB12, 0); in wb45n_gpio_hw_init()
81 int rc = 0; in board_eth_init()
84 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); in board_eth_init()
92 return 0; in board_early_init_f()
98 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
[all …]
/openbmc/u-boot/board/atmel/at91sam9x5ek/
H A Dat91sam9x5ek.c45 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | in at91sam9x5ek_nand_hw_init()
46 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), in at91sam9x5ek_nand_hw_init()
70 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ in at91sam9x5ek_nand_hw_init()
92 return 0; in board_late_init()
109 return 0; in board_early_init_f()
119 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
128 return 0; in board_init()
135 return 0; in dram_init()
162 ddr2->rtr = 0x411; in ddr2_conf()
/openbmc/u-boot/board/atmel/sama5d3xek/
H A Dsama5d3xek.c69 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | in sama5d3xek_nor_hw_init()
70 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), in sama5d3xek_nor_hw_init()
71 &smc->cs[0].setup); in sama5d3xek_nor_hw_init()
74 &smc->cs[0].pulse); in sama5d3xek_nor_hw_init()
76 &smc->cs[0].cycle); in sama5d3xek_nor_hw_init()
77 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | in sama5d3xek_nor_hw_init()
78 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | in sama5d3xek_nor_hw_init()
79 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| in sama5d3xek_nor_hw_init()
80 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); in sama5d3xek_nor_hw_init()
85 &smc->cs[0].mode); in sama5d3xek_nor_hw_init()
[all …]
/openbmc/u-boot/board/atmel/at91sam9n12ek/
H A Dat91sam9n12ek.c49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | in at91sam9n12ek_nand_hw_init()
50 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), in at91sam9n12ek_nand_hw_init()
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ in at91sam9n12ek_nand_hw_init()
86 .vl_sync = 0,
99 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ in lcd_enable()
121 dram_size = 0; in lcd_show_board_info()
122 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) in lcd_show_board_info()
124 nand_size = 0; in lcd_show_board_info()
125 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) in lcd_show_board_info()
139 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | in at91sam9n12ek_ks8851_hw_init()
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dau8522_priv.h27 #define AU8522_ANALOG_MODE 0
88 #define AU8522_INPUT_CONTROL_REG081H 0x081
89 #define AU8522_PGA_CONTROL_REG082H 0x082
90 #define AU8522_CLAMPING_CONTROL_REG083H 0x083
92 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
93 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
94 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
95 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
96 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
97 #define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/openbmc/linux/drivers/ata/
H A Dsata_qstor.c39 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
40 QS_HID_HPHY = 0x0004, /* host physical interface info */
41 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
42 QS_HST_SFF = 0x0100, /* host status fifo offset */
43 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
47 QS_CNFG3_GSRST = 0x01, /* global chip reset */
48 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
51 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
52 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
53 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]
/openbmc/linux/drivers/platform/x86/
H A Dfujitsu-laptop.c54 #define FUJITSU_DRIVER_VERSION "0.6.0"
66 #define ACPI_FUJITSU_NOTIFY_CODE 0x80
70 #define FUNC_LEDS (BIT(12) | BIT(0))
75 #define UNSUPPORTED_CMD 0x80000000
86 #define FUNC_LED_OFF BIT(0)
87 #define FUNC_LED_ON (BIT(0) | BIT(16) | BIT(17))
97 #define BACKLIGHT_OFF (BIT(0) | BIT(1))
98 #define BACKLIGHT_ON 0
101 #define KEY1_CODE 0x410
102 #define KEY2_CODE 0x411
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lcn.c66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
[all …]
/openbmc/linux/sound/pci/lx6464es/
H A Dlx_core.c23 0,
24 0x400,
25 0x401,
26 0x402,
27 0x403,
28 0x404,
29 0x405,
30 0x406,
31 0x407,
32 0x408,
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]

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