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/openbmc/linux/arch/m68k/fpsp040/
H A Dstan.S27 | k = N mod 2, so in particular, k = 0 or 1.
62 BOUNDS1: .long 0x3FD78000,0x4004BC7E
63 TWOBYPI: .long 0x3FE45F30,0x6DC9C883
65 TANQ4: .long 0x3EA0B759,0xF50F8688
66 TANP3: .long 0xBEF2BAA5,0xA8924F04
68 TANQ3: .long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000
70 TANP2: .long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000
72 TANQ2: .long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000
74 TANP1: .long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000
76 TANQ1: .long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000
[all …]
H A Dget_op.S9 | determines the opclass (0, 2, or 3) and branches to the
17 | - For unnormalized numbers (opclass 0, 2, or 3) the
23 | - For denormalized numbers (opclass 0 or 2) the number(s) is not
71 .long 0x40000000,0xc90fdaa2,0x2168c235 |pi
73 .long 0x40000000,0xc90fdaa2,0x2168c234 |pi
75 .long 0x40000000,0xc90fdaa2,0x2168c235 |pi
79 .long 0x3ffd0000,0x9a209a84,0xfbcff798 |log10(2)
80 .long 0x40000000,0xadf85458,0xa2bb4a9a |e
81 .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc |log2(e)
82 .long 0x3ffd0000,0xde5bd8a9,0x37287195 |log10(e)
[all …]
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DKconfig17 default 0x40a00000
21 default 0x40400000
34 default 0x03800000
38 default 0x83800000
42 default 0x2
46 default 0x1
66 default 0x40020000
70 default 0x40060000
74 default 0x401f4000
78 default 0x401f8000
/openbmc/linux/arch/m68k/configs/
H A Dm5208evb_defconfig15 CONFIG_RAMBASE=0x40000000
16 CONFIG_RAMSIZE=0x2000000
17 CONFIG_VECTORBASE=0x40000000
18 CONFIG_KERNELBASE=0x40020000
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra.h10 #define NV_PA_ARM_PERIPHBASE 0x50040000
11 #define NV_PA_PG_UP_BASE 0x60000000
12 #define NV_PA_TMRUS_BASE 0x60005010
13 #define NV_PA_CLK_RST_BASE 0x60006000
14 #define NV_PA_FLOW_BASE 0x60007000
15 #define NV_PA_GPIO_BASE 0x6000D000
16 #define NV_PA_EVP_BASE 0x6000F000
17 #define NV_PA_APB_MISC_BASE 0x70000000
18 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
H A Dstm32f7-pinctrl.dtsi15 ranges = <0 0x40020000 0x3000>;
17 st,syscfg = <&syscfg 0x8>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
34 reg = <0x400 0x400>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
44 reg = <0x800 0x400>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
54 reg = <0xc00 0x400>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
[all …]
H A Dste-dbx5x0.dtsi40 #size-cells = <0>;
56 reg = <0x300>;
65 reg = <0x301>;
81 polling-delay = <0>;
93 hysteresis = <0>;
121 /* The first (always on) ESRAM 0, 128 KB */
123 reg = <0x40000000 0x20000>;
126 ranges = <0 0x40000000 0x20000>;
128 sram@0 {
130 reg = <0x0 0x10000>;
[all …]
H A Dstm32f4-pinctrl.dtsi51 ranges = <0 0x40020000 0x3000>;
53 st,syscfg = <&syscfg 0x8>;
60 reg = <0x0 0x400>;
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
70 reg = <0x400 0x400>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
80 reg = <0x800 0x400>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
90 reg = <0xc00 0x400>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
[all …]
/openbmc/qemu/hw/arm/
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Dstm32f100_soc.c39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
40 0x40004800 };
41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn()
58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize()
[all …]
H A Dmsf2-soc.c35 #define MSF2_TIMER_BASE 0x40004000
36 #define MSF2_SYSREG_BASE 0x40038000
37 #define MSF2_EMAC_BASE 0x40041000
39 #define ENVM_BASE_ADDRESS 0x60000000
41 #define SRAM_BASE_ADDRESS 0x20000000
54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn()
78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn()
79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Darmsse.c54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt26 - 0 for active high
49 ranges = <0 0x40020000 0x3000>;
55 reg = <0x0 0x400>;
56 resets = <&reset_ahb1 0>;
83 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
84 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
86 * 0 : GPIO IN
87 * 1 : Alternate Function 0
106 < 0 > : Low speed
115 usart1_pins_a: usart1@0 {
[all …]
/openbmc/u-boot/include/configs/
H A Dastro_mcf5373l.h28 #define ASTRO_ID 0xF8
30 #define ASTRO_ID 0xFA
32 #define ASTRO_ID 0xF9
34 #define ASTRO_ID 0xFC
36 #define ASTRO_ID 0xFB
50 #define ENABLE_JFFS 0
66 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
67 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
79 #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000
80 #define CONFIG_SYS_CORE_SRAM 0x80000000
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
116 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml54 - description: The field mask of IRQ mux, needed if different of 0xf
61 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
64 '^gpio@[0-9a-f]*$':
114 minimum: 0
118 "^(.+-hog(-[0-9]+)?)$":
130 '-[0-9]*$':
152 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
153 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
155 * 0 : GPIO
156 * 1 : Alternate Function 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f746.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
89 #size-cells = <0>;
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
[all …]
H A Dstm32f4-pinctrl.dtsi52 ranges = <0 0x40020000 0x3000>;
54 st,syscfg = <&syscfg 0x8>;
62 reg = <0x0 0x400>;
63 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
72 reg = <0x400 0x400>;
73 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
82 reg = <0x800 0x400>;
83 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
92 reg = <0xc00 0x400>;
93 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
[all …]
/openbmc/linux/arch/m68k/ifpsp060/
H A Dfpsp.sa1 .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000
2 .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000
3 .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000
4 .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000
5 .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc
6 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
7 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
8 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
9 .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f
10 .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930
[all …]
/openbmc/linux/drivers/ata/
H A Dahci_tegra.c27 #define SATA_CONFIGURATION_0 0x180
28 #define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
31 #define SCFG_OFFSET 0x1000
33 #define T_SATA0_CFG_1 0x04
34 #define T_SATA0_CFG_1_IO_SPACE BIT(0)
39 #define T_SATA0_CFG_9 0x24
40 #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
42 #define SATA_FPCI_BAR5 0x94
43 #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
44 #define SATA_FPCI_BAR5_START (0x0040020 << 4)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]

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