Lines Matching +full:0 +full:x40020000
56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
89 #size-cells = <0>;
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
100 reg = <0x40011000 0x400>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
109 reg = <0x40007000 0x400>;
116 reg = <0x40023800 0x400>;
126 ranges = <0 0x40020000 0x3000>;
134 reg = <0x0 0x400>;
135 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
144 reg = <0x400 0x400>;
145 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
155 reg = <0x800 0x400>;
156 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
165 reg = <0xc00 0x400>;
166 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
175 reg = <0x1000 0x400>;
176 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
185 reg = <0x1400 0x400>;
186 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
195 reg = <0x1800 0x400>;
196 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
205 reg = <0x1c00 0x400>;
206 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
215 reg = <0x2000 0x400>;
216 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
225 reg = <0x2400 0x400>;
226 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
235 reg = <0x2800 0x400>;
236 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
241 sdio_pins: sdio_pins@0 {
254 sdio_pins_od: sdio_pins_od@0 {
272 sdio_pins_b: sdio_pins_b@0 {
285 sdio_pins_od_b: sdio_pins_od_b@0 {
306 reg = <0x40012c00 0x400>;
307 clocks = <&rcc 0 171>;
310 pinctrl-0 = <&sdio_pins>;
318 reg = <0x40011c00 0x400>;
319 clocks = <&rcc 0 167>;
322 pinctrl-0 = <&sdio_pins_b>;
330 reg = <0x40000c00 0x400>;
332 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
337 reg = <0x40016800 0x200>;
339 clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;