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Searched +full:0 +full:x40012000 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt44 - #size-cells = <0>;
60 - reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
64 - interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
68 from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
73 from 0 to 19 on stm32h7)
99 reg = <0x40012000 0x400>;
101 clocks = <&rcc 0 168>;
106 pinctrl-0 = <&adc3_in8_pin>;
110 #size-cells = <0>;
112 adc@0 {
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32f205_soc.c36 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
37 0x40000800, 0x40000C00 };
38 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
39 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
40 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
41 0x40012200 };
42 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
43 0x40003C00 };
59 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f205_soc_initfn()
64 for (i = 0; i < STM_NUM_TIMERS; i++) { in stm32f205_soc_initfn()
[all …]
H A Dmsf2-soc.c35 #define MSF2_TIMER_BASE 0x40004000
36 #define MSF2_SYSREG_BASE 0x40038000
37 #define MSF2_EMAC_BASE 0x40041000
39 #define ENVM_BASE_ADDRESS 0x60000000
41 #define SRAM_BASE_ADDRESS 0x20000000
54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn()
78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn()
79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Darmsse.c54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml94 const: 0
228 "^adc@[0-9]+$":
245 - 0x0: ADC1
246 - 0x100: ADC2
247 - 0x200: ADC3 (stm32f4 only)
257 const: 0
262 - 0 for adc@0 (single adc for stm32mp13)
289 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
290 - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
291 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
[all …]
H A Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]