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/openbmc/u-boot/include/configs/
H A Dcolibri_pxa270.h17 #define CONFIG_BOARD_SIZE_LIMIT 0x40000
29 "if fatload mmc 0 0xa0000000 uImage; then " \
30 "bootm 0xa0000000; " \
32 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
33 "bootm 0xa0000000; " \
35 "bootm 0xc0000;"
69 #define CONFIG_DM9000_BASE 0x08000000
82 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
87 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
88 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
[all …]
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dsmdkc100.h30 #define CONFIG_SYS_SDRAM_BASE 0x30000000
40 * 1MB = 0x100000, 0x100000 = 1024 * 1024
64 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
65 " onenand write 0x32008000 0x0 0x40000\0"
71 "onenand erase 0x60000 0x300000;" \
72 "onenand write 0x31008000 0x60000 0x300000\0" \
75 "onenand write 0x32000000 0x1260000 0x8C0000\0" \
77 "onenand read 0x30007FC0 0x60000 0x300000;" \
78 "bootm 0x30007FC0\0" \
83 "run bootk\0" \
[all …]
H A Dwork_92105.h68 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
121 #define CONFIG_ENV_SIZE 0x00020000
122 #define CONFIG_ENV_OFFSET 0x00100000
123 #define CONFIG_ENV_OFFSET_REDUND 0x00120000
124 #define CONFIG_ENV_ADDR 0x80000100
134 #define CONFIG_LOADADDR 0x80008000
140 /* SPL will be executed at offset 0 */
141 #define CONFIG_SPL_TEXT_BASE 0x00000000
143 #define CONFIG_SPL_STACK 0x0000FFF8
146 /* SPL will load U-Boot from NAND offset 0x40000 */
[all …]
H A Dap121.h15 #define CONFIG_SYS_MALLOC_LEN 0x40000
16 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
18 #define CONFIG_SYS_SDRAM_BASE 0x80000000
19 #define CONFIG_SYS_LOAD_ADDR 0x81000000
21 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
22 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000
31 "bootm 0x9f650000"
33 #define CONFIG_ENV_OFFSET 0x40000
34 #define CONFIG_ENV_SECT_SIZE 0x10000
35 #define CONFIG_ENV_SIZE 0x10000
[all …]
H A Dap143.h15 #define CONFIG_SYS_MALLOC_LEN 0x40000
16 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
18 #define CONFIG_SYS_SDRAM_BASE 0x80000000
19 #define CONFIG_SYS_LOAD_ADDR 0x81000000
21 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
22 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000
35 "bootm 0x9f680000"
37 #define CONFIG_ENV_OFFSET 0x40000
38 #define CONFIG_ENV_SECT_SIZE 0x10000
39 #define CONFIG_ENV_SIZE 0x10000
[all …]
H A Dmx31pdk.h28 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
61 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
63 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
64 "bootcmd=run bootcmd_net\0" \
66 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
67 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
68 "nand erase 0x0 0x40000; " \
69 "nand write 0x81000000 0x0 0x40000\0"
76 #define CONFIG_SYS_MEMTEST_START 0x80000000
77 #define CONFIG_SYS_MEMTEST_END 0x80010000
[all …]
/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))
22 #define UCD_BIST_STATUS 0x12C0070
23 #define NPS_CORE_BIST_REG 0x10000E8
24 #define NPS_CORE_NPC_BIST_REG 0x1000128
25 #define NPS_PKT_SLC_BIST_REG 0x1040088
26 #define NPS_PKT_IN_BIST_REG 0x1040100
27 #define POM_BIST_REG 0x11C0100
28 #define BMI_BIST_REG 0x1140080
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400))
30 #define EFL_TOP_BIST_STAT 0x1241090
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5cm.dtsi11 reg = <0x20000000 0x8000000>;
27 timer@0 {
29 reg = <0>;
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
59 pinctrl-0 = <&pinctrl_nand_oe_we
65 reg = <0x3 0x0 0x800000>;
80 at91bootstrap@0 {
82 reg = <0x0 0x40000>;
87 reg = <0x40000 0xc0000>;
[all …]
H A Daks-cdu.dts33 rs485-rts-delay = <0 0>;
39 rs485-rts-delay = <0 0>;
45 rs485-rts-delay = <0 0>;
68 bootstrap@0 {
70 reg = <0x0 0x40000>;
75 reg = <0x40000 0x80000>;
80 reg = <0xc0000 0x40000>;
85 reg = <0x100000 0x400000>;
90 reg = <0x500000 0x7b00000>;
H A Dat91-sam9x60ek.dts40 pinctrl-0 = <&pinctrl_key_gpio_default>;
53 pinctrl-0 = <&pinctrl_gpio_leds>;
110 pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
116 pinctrl-0 = <&pinctrl_can0_rx_tx>;
122 pinctrl-0 = <&pinctrl_can1_rx_tx>;
128 pinctrl-0 = <&pinctrl_classd_default>;
136 pinctrl-0 = <&pinctrl_dbgu>;
142 pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
147 pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
151 reg = <0x3 0x0 0x800000>;
[all …]
H A Dat91-sama5d4_xplained.dts21 reg = <0x20000000 0x20000000>;
51 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
62 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
66 slot@0 {
67 reg = <0>;
69 cd-gpios = <&pioE 3 0>;
86 cs-gpios = <&pioB 21 0>;
91 timer0: timer@0 {
93 reg = <0>;
104 pinctrl-0 = <
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dopen-pic.txt26 address. The type shall be <u32> and the value shall be 0. As such,
45 0 = low-to-high edge triggered
63 #address-cells = <0>;
68 // Offset address of 0x40000 and size of 0x40000.
69 reg = <0x40000 0x40000>;
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3-nor.dtso13 fragment@0 {
17 #size-cells = <0>;
18 flash@0 {
20 reg = <0>;
28 partition@0 {
30 reg = <0x0 0x40000>;
36 reg = <0x40000 0x40000>;
41 reg = <0x80000 0x80000>;
46 reg = <0x100000 0x80000>;
52 reg = <0x180000 0xa80000>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
49 reg = <0x41100 0x100 0x41300 4>;
50 interrupts = <0 0 3 0
51 1 0 3 0
52 2 0 3 0
53 3 0 3 0>;
58 reg = <0x41400 0x200>;
60 0xb0 2 0 0
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44140 4>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1046a.dtsi18 #clock-cells = <0>;
27 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
28 <0x0 0x1420000 0 0x10000>, /* GICC */
29 <0x0 0x1440000 0 0x20000>, /* GICH */
30 <0x0 0x1460000 0 0x20000>; /* GICV */
31 interrupts = <1 9 0xf08>;
42 reg = <0x0 0x1ee1000 0x0 0x1000>;
50 #size-cells = <0>;
51 reg = <0x0 0x2100000 0x0 0x10000>;
52 interrupts = <0 64 0x4>;
[all …]
H A Dfsl-ls1088a.dtsi16 reg = <0x00000000 0x80000000 0 0x80000000>;
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
26 interrupts = <1 9 0x4>;
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml168 reg = <0x10000000 0x40000>,
169 <0x30000000 0x40000>,
170 <0x38000000 0x10000>;
174 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
182 reg = <0x10000000 0x40000>,
183 <0x30000000 0x40000>,
184 <0x38000000 0x10000>;
188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
[all …]
/openbmc/u-boot/configs/
H A Dsmdkc100_defconfig3 CONFIG_SYS_TEXT_BASE=0x34800000
9 …n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x3…
20 …RTS_DEFAULT="mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x3…
26 CONFIG_SMC911X_BASE=0x98800300
/openbmc/linux/arch/powerpc/boot/dts/
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
/openbmc/qemu/docs/specs/
H A Dedu.rst34 PCI Region 0:
41 Only ``size == 4`` accesses are allowed for addresses ``< 0x80``.
44 0x00 (RO) : identification
45 Value is in the form ``0xRRrr00edu`` where:
49 0x04 (RW) : card liveness check
52 0x08 (RW) : factorial computation
54 This happens only after factorial bit in the status register (0x20
57 0x20 (RW) : status register
60 0x01
62 0x80
[all …]

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