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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-kp-ddc.dts16 pwms = <&pwm2 0 50000>;
18 brightness-levels = <0 24 28 32 36
28 #size-cells = <0>;
31 pinctrl-0 = <&pinctrl_disp>;
33 port@0 {
34 reg = <0>;
78 reg = <0x48>;
80 #size-cells = <0>;
97 reg = <0x21>;
108 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h12 #define LCD_CONTROL (0x4 * 0x000)
13 #define LCD_CTRL_PROGRESSIVE (0 << 0)
14 #define LCD_CTRL_INTERLACED BIT(0)
20 #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6)
24 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8)
28 #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10)
32 #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12)
37 #define LCD_CTRL_CONTINUOUS (0 << 15)
42 #define LCD_CTRL_OUTPUT_DISABLED (0 << 19)
49 #define LCD_CTRL_ALPHA_ALL (0xff << 6)
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h17 unsigned char res1[0x4];
64 unsigned char res2[0x8];
66 unsigned char res3[0x8];
68 unsigned char res4[0xDF00];
70 unsigned char res5[0xC];
72 unsigned char res6[0xC];
74 unsigned char res7[0xC];
76 unsigned char res8[0xC];
78 unsigned char res9[0xC];
80 unsigned char res10[0xAC];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h12 { "pbl", 0x0, 0x80000000 }, /* PBL */
13 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
14 { "qdma", 0x0, 0x800000 }, /* qDMA */
15 { "edma", 0x0, 0x400000 }, /* eDMA */
16 { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
17 { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
18 { "sata", 0x0, 0x8000 }, /* SATA */
19 { "sec", 0x0, 0x200 }, /* SEC */
20 { "dcu", 0x0, 0x2 }, /* Display controller Unit */
21 { "qe", 0x0, 0x1 }, /* QUICC Engine */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h17 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
18 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
19 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
20 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
25 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
26 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtscs454.h9 #define VIRT_BASE 0x00
10 #define PAGE_LEN 0x100
15 #define R_PAGESEL 0x0
16 #define R_RESET VIRT_ADDR(0x0, 0x1)
17 #define R_IRQEN VIRT_ADDR(0x0, 0x2)
18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
19 #define R_IRQSTAT VIRT_ADDR(0x0, 0x4)
20 #define R_DEVADD0 VIRT_ADDR(0x0, 0x6)
21 #define R_DEVID VIRT_ADDR(0x0, 0x8)
22 #define R_DEVREV VIRT_ADDR(0x0, 0x9)
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-xp.c31 V_MV78230 = BIT(0),
43 MPP_MODE(0,
44 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
45 MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
46 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
48 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
49 MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
50 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
52 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
53 MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
[all …]
/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S40 pshufd $0, t, t;
42 #define K(x0, x1, x2, x3, x4, i) \ argument
43 get_key(i, 0, x4); \
46 pxor x4, x0; \
49 get_key(i, 3, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
53 movdqa x0, x4; \
55 psrld $(32 - 13), x4; \
56 por x4, x0; \
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dhardware.c29 {HPHW_NPROC,0x01,0x4,0x0,"Indigo (840, 930)"},
30 {HPHW_NPROC,0x8,0x4,0x01,"Firefox(825,925)"},
31 {HPHW_NPROC,0xA,0x4,0x01,"Top Gun (835,834,935,635)"},
32 {HPHW_NPROC,0xB,0x4,0x01,"Technical Shogun (845, 645)"},
33 {HPHW_NPROC,0xF,0x4,0x01,"Commercial Shogun (949)"},
34 {HPHW_NPROC,0xC,0x4,0x01,"Cheetah (850, 950)"},
35 {HPHW_NPROC,0x80,0x4,0x01,"Cheetah (950S)"},
36 {HPHW_NPROC,0x81,0x4,0x01,"Jaguar (855, 955)"},
37 {HPHW_NPROC,0x82,0x4,0x01,"Cougar (860, 960)"},
38 {HPHW_NPROC,0x83,0x4,0x13,"Panther (865, 870, 980)"},
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb/
H A Daf9005-script.h19 {0xa180, 0x0, 0x8, 0xa},
20 {0xa181, 0x0, 0x8, 0xd7},
21 {0xa182, 0x0, 0x8, 0xa3},
22 {0xa0a0, 0x0, 0x8, 0x0},
23 {0xa0a1, 0x0, 0x5, 0x0},
24 {0xa0a1, 0x5, 0x1, 0x1},
25 {0xa0c0, 0x0, 0x4, 0x1},
26 {0xa20e, 0x4, 0x4, 0xa},
27 {0xa20f, 0x0, 0x8, 0x40},
28 {0xa210, 0x0, 0x8, 0x8},
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-f2xm1.c14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L },
15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L },
16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L },
17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L },
18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L },
19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L },
20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L },
21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L },
22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L },
23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L },
[all …]

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