Lines Matching +full:0 +full:x4
9 #define VIRT_BASE 0x00
10 #define PAGE_LEN 0x100
15 #define R_PAGESEL 0x0
16 #define R_RESET VIRT_ADDR(0x0, 0x1)
17 #define R_IRQEN VIRT_ADDR(0x0, 0x2)
18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
19 #define R_IRQSTAT VIRT_ADDR(0x0, 0x4)
20 #define R_DEVADD0 VIRT_ADDR(0x0, 0x6)
21 #define R_DEVID VIRT_ADDR(0x0, 0x8)
22 #define R_DEVREV VIRT_ADDR(0x0, 0x9)
23 #define R_PLLSTAT VIRT_ADDR(0x0, 0x0A)
24 #define R_PLL1CTL VIRT_ADDR(0x0, 0x0B)
25 #define R_PLL1RDIV VIRT_ADDR(0x0, 0x0C)
26 #define R_PLL1ODIV VIRT_ADDR(0x0, 0x0D)
27 #define R_PLL1FDIVL VIRT_ADDR(0x0, 0x0E)
28 #define R_PLL1FDIVH VIRT_ADDR(0x0, 0x0F)
29 #define R_PLL2CTL VIRT_ADDR(0x0, 0x10)
30 #define R_PLL2RDIV VIRT_ADDR(0x0, 0x11)
31 #define R_PLL2ODIV VIRT_ADDR(0x0, 0x12)
32 #define R_PLL2FDIVL VIRT_ADDR(0x0, 0x13)
33 #define R_PLL2FDIVH VIRT_ADDR(0x0, 0x14)
34 #define R_PLLCTL VIRT_ADDR(0x0, 0x15)
35 #define R_ISRC VIRT_ADDR(0x0, 0x16)
36 #define R_SCLKCTL VIRT_ADDR(0x0, 0x18)
37 #define R_TIMEBASE VIRT_ADDR(0x0, 0x19)
38 #define R_I2SP1CTL VIRT_ADDR(0x0, 0x1A)
39 #define R_I2SP2CTL VIRT_ADDR(0x0, 0x1B)
40 #define R_I2SP3CTL VIRT_ADDR(0x0, 0x1C)
41 #define R_I2S1MRATE VIRT_ADDR(0x0, 0x1D)
42 #define R_I2S2MRATE VIRT_ADDR(0x0, 0x1E)
43 #define R_I2S3MRATE VIRT_ADDR(0x0, 0x1F)
44 #define R_I2SCMC VIRT_ADDR(0x0, 0x20)
45 #define R_MCLK2PINC VIRT_ADDR(0x0, 0x21)
46 #define R_I2SPINC0 VIRT_ADDR(0x0, 0x22)
47 #define R_I2SPINC1 VIRT_ADDR(0x0, 0x23)
48 #define R_I2SPINC2 VIRT_ADDR(0x0, 0x24)
49 #define R_GPIOCTL0 VIRT_ADDR(0x0, 0x25)
50 #define R_GPIOCTL1 VIRT_ADDR(0x0, 0x26)
51 #define R_ASRC VIRT_ADDR(0x0, 0x28)
52 #define R_TDMCTL0 VIRT_ADDR(0x0, 0x2D)
53 #define R_TDMCTL1 VIRT_ADDR(0x0, 0x2E)
54 #define R_PCMP2CTL0 VIRT_ADDR(0x0, 0x2F)
55 #define R_PCMP2CTL1 VIRT_ADDR(0x0, 0x30)
56 #define R_PCMP3CTL0 VIRT_ADDR(0x0, 0x31)
57 #define R_PCMP3CTL1 VIRT_ADDR(0x0, 0x32)
58 #define R_PWRM0 VIRT_ADDR(0x0, 0x33)
59 #define R_PWRM1 VIRT_ADDR(0x0, 0x34)
60 #define R_PWRM2 VIRT_ADDR(0x0, 0x35)
61 #define R_PWRM3 VIRT_ADDR(0x0, 0x36)
62 #define R_PWRM4 VIRT_ADDR(0x0, 0x37)
63 #define R_I2SIDCTL VIRT_ADDR(0x0, 0x38)
64 #define R_I2SODCTL VIRT_ADDR(0x0, 0x39)
65 #define R_AUDIOMUX1 VIRT_ADDR(0x0, 0x3A)
66 #define R_AUDIOMUX2 VIRT_ADDR(0x0, 0x3B)
67 #define R_AUDIOMUX3 VIRT_ADDR(0x0, 0x3C)
68 #define R_HSDCTL1 VIRT_ADDR(0x1, 0x1)
69 #define R_HSDCTL2 VIRT_ADDR(0x1, 0x2)
70 #define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
71 #define R_HSDDELAY VIRT_ADDR(0x1, 0x4)
72 #define R_BUTCTL VIRT_ADDR(0x1, 0x5)
73 #define R_CH0AIC VIRT_ADDR(0x1, 0x6)
74 #define R_CH1AIC VIRT_ADDR(0x1, 0x7)
75 #define R_CH2AIC VIRT_ADDR(0x1, 0x8)
76 #define R_CH3AIC VIRT_ADDR(0x1, 0x9)
77 #define R_ICTL0 VIRT_ADDR(0x1, 0x0A)
78 #define R_ICTL1 VIRT_ADDR(0x1, 0x0B)
79 #define R_MICBIAS VIRT_ADDR(0x1, 0x0C)
80 #define R_PGACTL0 VIRT_ADDR(0x1, 0x0D)
81 #define R_PGACTL1 VIRT_ADDR(0x1, 0x0E)
82 #define R_PGACTL2 VIRT_ADDR(0x1, 0x0F)
83 #define R_PGACTL3 VIRT_ADDR(0x1, 0x10)
84 #define R_PGAZ VIRT_ADDR(0x1, 0x11)
85 #define R_ICH0VOL VIRT_ADDR(0x1, 0x12)
86 #define R_ICH1VOL VIRT_ADDR(0x1, 0x13)
87 #define R_ICH2VOL VIRT_ADDR(0x1, 0x14)
88 #define R_ICH3VOL VIRT_ADDR(0x1, 0x15)
89 #define R_ASRCILVOL VIRT_ADDR(0x1, 0x16)
90 #define R_ASRCIRVOL VIRT_ADDR(0x1, 0x17)
91 #define R_ASRCOLVOL VIRT_ADDR(0x1, 0x18)
92 #define R_ASRCORVOL VIRT_ADDR(0x1, 0x19)
93 #define R_IVOLCTLU VIRT_ADDR(0x1, 0x1C)
94 #define R_ALCCTL0 VIRT_ADDR(0x1, 0x1D)
95 #define R_ALCCTL1 VIRT_ADDR(0x1, 0x1E)
96 #define R_ALCCTL2 VIRT_ADDR(0x1, 0x1F)
97 #define R_ALCCTL3 VIRT_ADDR(0x1, 0x20)
98 #define R_NGATE VIRT_ADDR(0x1, 0x21)
99 #define R_DMICCTL VIRT_ADDR(0x1, 0x22)
100 #define R_DACCTL VIRT_ADDR(0x2, 0x1)
101 #define R_SPKCTL VIRT_ADDR(0x2, 0x2)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
103 #define R_DCCTL VIRT_ADDR(0x2, 0x4)
104 #define R_OVOLCTLU VIRT_ADDR(0x2, 0x6)
105 #define R_MUTEC VIRT_ADDR(0x2, 0x7)
106 #define R_MVOLL VIRT_ADDR(0x2, 0x8)
107 #define R_MVOLR VIRT_ADDR(0x2, 0x9)
108 #define R_HPVOLL VIRT_ADDR(0x2, 0x0A)
109 #define R_HPVOLR VIRT_ADDR(0x2, 0x0B)
110 #define R_SPKVOLL VIRT_ADDR(0x2, 0x0C)
111 #define R_SPKVOLR VIRT_ADDR(0x2, 0x0D)
112 #define R_SUBVOL VIRT_ADDR(0x2, 0x10)
113 #define R_COP0 VIRT_ADDR(0x2, 0x11)
114 #define R_COP1 VIRT_ADDR(0x2, 0x12)
115 #define R_COPSTAT VIRT_ADDR(0x2, 0x13)
116 #define R_PWM0 VIRT_ADDR(0x2, 0x14)
117 #define R_PWM1 VIRT_ADDR(0x2, 0x15)
118 #define R_PWM2 VIRT_ADDR(0x2, 0x16)
119 #define R_PWM3 VIRT_ADDR(0x2, 0x17)
120 #define R_HPSW VIRT_ADDR(0x2, 0x18)
121 #define R_THERMTS VIRT_ADDR(0x2, 0x19)
122 #define R_THERMSPK1 VIRT_ADDR(0x2, 0x1A)
123 #define R_THERMSTAT VIRT_ADDR(0x2, 0x1B)
124 #define R_SCSTAT VIRT_ADDR(0x2, 0x1C)
125 #define R_SDMON VIRT_ADDR(0x2, 0x1D)
126 #define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128 #define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130 #define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131 #define R_SPKCRRDM VIRT_ADDR(0x3, 0x6)
132 #define R_SPKCRRDH VIRT_ADDR(0x3, 0x7)
133 #define R_SPKCRADD VIRT_ADDR(0x3, 0x8)
134 #define R_SPKCRS VIRT_ADDR(0x3, 0x9)
135 #define R_SPKMBCEN VIRT_ADDR(0x3, 0x0A)
136 #define R_SPKMBCCTL VIRT_ADDR(0x3, 0x0B)
137 #define R_SPKMBCMUG1 VIRT_ADDR(0x3, 0x0C)
138 #define R_SPKMBCTHR1 VIRT_ADDR(0x3, 0x0D)
139 #define R_SPKMBCRAT1 VIRT_ADDR(0x3, 0x0E)
140 #define R_SPKMBCATK1L VIRT_ADDR(0x3, 0x0F)
141 #define R_SPKMBCATK1H VIRT_ADDR(0x3, 0x10)
142 #define R_SPKMBCREL1L VIRT_ADDR(0x3, 0x11)
143 #define R_SPKMBCREL1H VIRT_ADDR(0x3, 0x12)
144 #define R_SPKMBCMUG2 VIRT_ADDR(0x3, 0x13)
145 #define R_SPKMBCTHR2 VIRT_ADDR(0x3, 0x14)
146 #define R_SPKMBCRAT2 VIRT_ADDR(0x3, 0x15)
147 #define R_SPKMBCATK2L VIRT_ADDR(0x3, 0x16)
148 #define R_SPKMBCATK2H VIRT_ADDR(0x3, 0x17)
149 #define R_SPKMBCREL2L VIRT_ADDR(0x3, 0x18)
150 #define R_SPKMBCREL2H VIRT_ADDR(0x3, 0x19)
151 #define R_SPKMBCMUG3 VIRT_ADDR(0x3, 0x1A)
152 #define R_SPKMBCTHR3 VIRT_ADDR(0x3, 0x1B)
153 #define R_SPKMBCRAT3 VIRT_ADDR(0x3, 0x1C)
154 #define R_SPKMBCATK3L VIRT_ADDR(0x3, 0x1D)
155 #define R_SPKMBCATK3H VIRT_ADDR(0x3, 0x1E)
156 #define R_SPKMBCREL3L VIRT_ADDR(0x3, 0x1F)
157 #define R_SPKMBCREL3H VIRT_ADDR(0x3, 0x20)
158 #define R_SPKCLECTL VIRT_ADDR(0x3, 0x21)
159 #define R_SPKCLEMUG VIRT_ADDR(0x3, 0x22)
160 #define R_SPKCOMPTHR VIRT_ADDR(0x3, 0x23)
161 #define R_SPKCOMPRAT VIRT_ADDR(0x3, 0x24)
162 #define R_SPKCOMPATKL VIRT_ADDR(0x3, 0x25)
163 #define R_SPKCOMPATKH VIRT_ADDR(0x3, 0x26)
164 #define R_SPKCOMPRELL VIRT_ADDR(0x3, 0x27)
165 #define R_SPKCOMPRELH VIRT_ADDR(0x3, 0x28)
166 #define R_SPKLIMTHR VIRT_ADDR(0x3, 0x29)
167 #define R_SPKLIMTGT VIRT_ADDR(0x3, 0x2A)
168 #define R_SPKLIMATKL VIRT_ADDR(0x3, 0x2B)
169 #define R_SPKLIMATKH VIRT_ADDR(0x3, 0x2C)
170 #define R_SPKLIMRELL VIRT_ADDR(0x3, 0x2D)
171 #define R_SPKLIMRELH VIRT_ADDR(0x3, 0x2E)
172 #define R_SPKEXPTHR VIRT_ADDR(0x3, 0x2F)
173 #define R_SPKEXPRAT VIRT_ADDR(0x3, 0x30)
174 #define R_SPKEXPATKL VIRT_ADDR(0x3, 0x31)
175 #define R_SPKEXPATKH VIRT_ADDR(0x3, 0x32)
176 #define R_SPKEXPRELL VIRT_ADDR(0x3, 0x33)
177 #define R_SPKEXPRELH VIRT_ADDR(0x3, 0x34)
178 #define R_SPKFXCTL VIRT_ADDR(0x3, 0x35)
179 #define R_DACEQFILT VIRT_ADDR(0x4, 0x1)
180 #define R_DACCRWDL VIRT_ADDR(0x4, 0x2)
181 #define R_DACCRWDM VIRT_ADDR(0x4, 0x3)
182 #define R_DACCRWDH VIRT_ADDR(0x4, 0x4)
183 #define R_DACCRRDL VIRT_ADDR(0x4, 0x5)
184 #define R_DACCRRDM VIRT_ADDR(0x4, 0x6)
185 #define R_DACCRRDH VIRT_ADDR(0x4, 0x7)
186 #define R_DACCRADD VIRT_ADDR(0x4, 0x8)
187 #define R_DACCRS VIRT_ADDR(0x4, 0x9)
188 #define R_DACMBCEN VIRT_ADDR(0x4, 0x0A)
189 #define R_DACMBCCTL VIRT_ADDR(0x4, 0x0B)
190 #define R_DACMBCMUG1 VIRT_ADDR(0x4, 0x0C)
191 #define R_DACMBCTHR1 VIRT_ADDR(0x4, 0x0D)
192 #define R_DACMBCRAT1 VIRT_ADDR(0x4, 0x0E)
193 #define R_DACMBCATK1L VIRT_ADDR(0x4, 0x0F)
194 #define R_DACMBCATK1H VIRT_ADDR(0x4, 0x10)
195 #define R_DACMBCREL1L VIRT_ADDR(0x4, 0x11)
196 #define R_DACMBCREL1H VIRT_ADDR(0x4, 0x12)
197 #define R_DACMBCMUG2 VIRT_ADDR(0x4, 0x13)
198 #define R_DACMBCTHR2 VIRT_ADDR(0x4, 0x14)
199 #define R_DACMBCRAT2 VIRT_ADDR(0x4, 0x15)
200 #define R_DACMBCATK2L VIRT_ADDR(0x4, 0x16)
201 #define R_DACMBCATK2H VIRT_ADDR(0x4, 0x17)
202 #define R_DACMBCREL2L VIRT_ADDR(0x4, 0x18)
203 #define R_DACMBCREL2H VIRT_ADDR(0x4, 0x19)
204 #define R_DACMBCMUG3 VIRT_ADDR(0x4, 0x1A)
205 #define R_DACMBCTHR3 VIRT_ADDR(0x4, 0x1B)
206 #define R_DACMBCRAT3 VIRT_ADDR(0x4, 0x1C)
207 #define R_DACMBCATK3L VIRT_ADDR(0x4, 0x1D)
208 #define R_DACMBCATK3H VIRT_ADDR(0x4, 0x1E)
209 #define R_DACMBCREL3L VIRT_ADDR(0x4, 0x1F)
210 #define R_DACMBCREL3H VIRT_ADDR(0x4, 0x20)
211 #define R_DACCLECTL VIRT_ADDR(0x4, 0x21)
212 #define R_DACCLEMUG VIRT_ADDR(0x4, 0x22)
213 #define R_DACCOMPTHR VIRT_ADDR(0x4, 0x23)
214 #define R_DACCOMPRAT VIRT_ADDR(0x4, 0x24)
215 #define R_DACCOMPATKL VIRT_ADDR(0x4, 0x25)
216 #define R_DACCOMPATKH VIRT_ADDR(0x4, 0x26)
217 #define R_DACCOMPRELL VIRT_ADDR(0x4, 0x27)
218 #define R_DACCOMPRELH VIRT_ADDR(0x4, 0x28)
219 #define R_DACLIMTHR VIRT_ADDR(0x4, 0x29)
220 #define R_DACLIMTGT VIRT_ADDR(0x4, 0x2A)
221 #define R_DACLIMATKL VIRT_ADDR(0x4, 0x2B)
222 #define R_DACLIMATKH VIRT_ADDR(0x4, 0x2C)
223 #define R_DACLIMRELL VIRT_ADDR(0x4, 0x2D)
224 #define R_DACLIMRELH VIRT_ADDR(0x4, 0x2E)
225 #define R_DACEXPTHR VIRT_ADDR(0x4, 0x2F)
226 #define R_DACEXPRAT VIRT_ADDR(0x4, 0x30)
227 #define R_DACEXPATKL VIRT_ADDR(0x4, 0x31)
228 #define R_DACEXPATKH VIRT_ADDR(0x4, 0x32)
229 #define R_DACEXPRELL VIRT_ADDR(0x4, 0x33)
230 #define R_DACEXPRELH VIRT_ADDR(0x4, 0x34)
231 #define R_DACFXCTL VIRT_ADDR(0x4, 0x35)
232 #define R_SUBEQFILT VIRT_ADDR(0x5, 0x1)
233 #define R_SUBCRWDL VIRT_ADDR(0x5, 0x2)
234 #define R_SUBCRWDM VIRT_ADDR(0x5, 0x3)
235 #define R_SUBCRWDH VIRT_ADDR(0x5, 0x4)
236 #define R_SUBCRRDL VIRT_ADDR(0x5, 0x5)
237 #define R_SUBCRRDM VIRT_ADDR(0x5, 0x6)
238 #define R_SUBCRRDH VIRT_ADDR(0x5, 0x7)
239 #define R_SUBCRADD VIRT_ADDR(0x5, 0x8)
240 #define R_SUBCRS VIRT_ADDR(0x5, 0x9)
241 #define R_SUBMBCEN VIRT_ADDR(0x5, 0x0A)
242 #define R_SUBMBCCTL VIRT_ADDR(0x5, 0x0B)
243 #define R_SUBMBCMUG1 VIRT_ADDR(0x5, 0x0C)
244 #define R_SUBMBCTHR1 VIRT_ADDR(0x5, 0x0D)
245 #define R_SUBMBCRAT1 VIRT_ADDR(0x5, 0x0E)
246 #define R_SUBMBCATK1L VIRT_ADDR(0x5, 0x0F)
247 #define R_SUBMBCATK1H VIRT_ADDR(0x5, 0x10)
248 #define R_SUBMBCREL1L VIRT_ADDR(0x5, 0x11)
249 #define R_SUBMBCREL1H VIRT_ADDR(0x5, 0x12)
250 #define R_SUBMBCMUG2 VIRT_ADDR(0x5, 0x13)
251 #define R_SUBMBCTHR2 VIRT_ADDR(0x5, 0x14)
252 #define R_SUBMBCRAT2 VIRT_ADDR(0x5, 0x15)
253 #define R_SUBMBCATK2L VIRT_ADDR(0x5, 0x16)
254 #define R_SUBMBCATK2H VIRT_ADDR(0x5, 0x17)
255 #define R_SUBMBCREL2L VIRT_ADDR(0x5, 0x18)
256 #define R_SUBMBCREL2H VIRT_ADDR(0x5, 0x19)
257 #define R_SUBMBCMUG3 VIRT_ADDR(0x5, 0x1A)
258 #define R_SUBMBCTHR3 VIRT_ADDR(0x5, 0x1B)
259 #define R_SUBMBCRAT3 VIRT_ADDR(0x5, 0x1C)
260 #define R_SUBMBCATK3L VIRT_ADDR(0x5, 0x1D)
261 #define R_SUBMBCATK3H VIRT_ADDR(0x5, 0x1E)
262 #define R_SUBMBCREL3L VIRT_ADDR(0x5, 0x1F)
263 #define R_SUBMBCREL3H VIRT_ADDR(0x5, 0x20)
264 #define R_SUBCLECTL VIRT_ADDR(0x5, 0x21)
265 #define R_SUBCLEMUG VIRT_ADDR(0x5, 0x22)
266 #define R_SUBCOMPTHR VIRT_ADDR(0x5, 0x23)
267 #define R_SUBCOMPRAT VIRT_ADDR(0x5, 0x24)
268 #define R_SUBCOMPATKL VIRT_ADDR(0x5, 0x25)
269 #define R_SUBCOMPATKH VIRT_ADDR(0x5, 0x26)
270 #define R_SUBCOMPRELL VIRT_ADDR(0x5, 0x27)
271 #define R_SUBCOMPRELH VIRT_ADDR(0x5, 0x28)
272 #define R_SUBLIMTHR VIRT_ADDR(0x5, 0x29)
273 #define R_SUBLIMTGT VIRT_ADDR(0x5, 0x2A)
274 #define R_SUBLIMATKL VIRT_ADDR(0x5, 0x2B)
275 #define R_SUBLIMATKH VIRT_ADDR(0x5, 0x2C)
276 #define R_SUBLIMRELL VIRT_ADDR(0x5, 0x2D)
277 #define R_SUBLIMRELH VIRT_ADDR(0x5, 0x2E)
278 #define R_SUBEXPTHR VIRT_ADDR(0x5, 0x2F)
279 #define R_SUBEXPRAT VIRT_ADDR(0x5, 0x30)
280 #define R_SUBEXPATKL VIRT_ADDR(0x5, 0x31)
281 #define R_SUBEXPATKH VIRT_ADDR(0x5, 0x32)
282 #define R_SUBEXPRELL VIRT_ADDR(0x5, 0x33)
283 #define R_SUBEXPRELH VIRT_ADDR(0x5, 0x34)
284 #define R_SUBFXCTL VIRT_ADDR(0x5, 0x35)
288 #define FM_PLLCTL_VCCI_PLL 0xC0
291 #define FM_PLLCTL_RZ_PLL 0x38
293 #define FB_PLLCTL_CP_PLL 0
294 #define FM_PLLCTL_CP_PLL 0x7
297 #define FB_PLLRDIV_REFDIV_PLL 0
298 #define FM_PLLRDIV_REFDIV_PLL 0xFF
301 #define FB_PLLODIV_OUTDIV_PLL 0
302 #define FM_PLLODIV_OUTDIV_PLL 0xFF
305 #define FB_PLLFDIVL_FBDIVL_PLL 0
306 #define FM_PLLFDIVL_FBDIVL_PLL 0xFF
309 #define FB_PLLFDIVH_FBDIVH_PLL 0
310 #define FM_PLLFDIVH_FBDIVH_PLL 0xF
314 #define FM_I2SPCTL_BCLKSTAT 0x80
315 #define FV_BCLKSTAT_LOST 0x80
316 #define FV_BCLKSTAT_NOT_LOST 0x0
319 #define FM_I2SPCTL_BCLKP 0x40
320 #define FV_BCLKP_NOT_INVERTED 0x0
321 #define FV_BCLKP_INVERTED 0x40
324 #define FM_I2SPCTL_PORTMS 0x20
325 #define FV_PORTMS_SLAVE 0x0
326 #define FV_PORTMS_MASTER 0x20
329 #define FM_I2SPCTL_LRCLKP 0x10
330 #define FV_LRCLKP_NOT_INVERTED 0x0
331 #define FV_LRCLKP_INVERTED 0x10
334 #define FM_I2SPCTL_WL 0xC
335 #define FV_WL_16 0x0
336 #define FV_WL_20 0x4
337 #define FV_WL_24 0x8
338 #define FV_WL_32 0xC
340 #define FB_I2SPCTL_FORMAT 0
341 #define FM_I2SPCTL_FORMAT 0x3
342 #define FV_FORMAT_RIGHT 0x0
343 #define FV_FORMAT_LEFT 0x1
344 #define FV_FORMAT_I2S 0x2
345 #define FV_FORMAT_TDM 0x3
349 #define FM_I2SMRATE_I2SMCLKHALF 0x80
350 #define FV_I2SMCLKHALF_I2S1MCLKDIV_DIV_2 0x0
351 #define FV_I2SMCLKHALF_I2S1MCLKDIV_ONLY 0x80
354 #define FM_I2SMRATE_I2SMCLKDIV 0x60
355 #define FV_I2SMCLKDIV_125 0x0
356 #define FV_I2SMCLKDIV_128 0x20
357 #define FV_I2SMCLKDIV_136 0x40
358 #define FV_I2SMCLKDIV_192 0x60
361 #define FM_I2SMRATE_I2SMBR 0x18
362 #define FV_I2SMBR_32 0x0
363 #define FV_I2SMBR_44PT1 0x8
364 #define FV_I2SMBR_48 0x10
365 #define FV_I2SMBR_MCLK_MODE 0x18
367 #define FB_I2SMRATE_I2SMBM 0
368 #define FM_I2SMRATE_I2SMBM 0x3
369 #define FV_I2SMBM_0PT25 0x0
370 #define FV_I2SMBM_0PT5 0x1
371 #define FV_I2SMBM_1 0x2
372 #define FV_I2SMBM_2 0x3
376 #define FM_PCMPCTL0_PCMFLENP 0x4
377 #define FV_PCMFLENP_128 0x0
378 #define FV_PCMFLENP_256 0x4
381 #define FM_PCMPCTL0_SLSYNCP 0x2
382 #define FV_SLSYNCP_SHORT 0x0
383 #define FV_SLSYNCP_LONG 0x2
385 #define FB_PCMPCTL0_BDELAYP 0
386 #define FM_PCMPCTL0_BDELAYP 0x1
387 #define FV_BDELAYP_NO_DELAY 0x0
388 #define FV_BDELAYP_1BCLK_DELAY 0x1
392 #define FM_PCMPCTL1_PCMMOMP 0x40
395 #define FM_PCMPCTL1_PCMSOP 0x20
396 #define FV_PCMSOP_1 0x0
397 #define FV_PCMSOP_2 0x20
400 #define FM_PCMPCTL1_PCMDSSP 0x18
401 #define FV_PCMDSSP_16 0x0
402 #define FV_PCMDSSP_24 0x8
403 #define FV_PCMDSSP_32 0x10
406 #define FM_PCMPCTL1_PCMMIMP 0x2
408 #define FB_PCMPCTL1_PCMSIP 0
409 #define FM_PCMPCTL1_PCMSIP 0x1
410 #define FV_PCMSIP_1 0x0
411 #define FV_PCMSIP_2 0x1
415 #define FM_CHAIC_MICBST 0x30
419 #define FM_PGACTL_PGAMUTE 0x80
421 #define FB_PGACTL_PGAVOL 0
422 #define FM_PGACTL_PGAVOL 0x3F
425 #define FB_ICHVOL_ICHVOL 0
426 #define FM_ICHVOL_ICHVOL 0xFF
430 #define FM_SPKMBCMUG_PHASE 0x20
432 #define FB_SPKMBCMUG_MUGAIN 0
433 #define FM_SPKMBCMUG_MUGAIN 0x1F
436 #define FB_SPKMBCTHR_THRESH 0
437 #define FM_SPKMBCTHR_THRESH 0xFF
440 #define FB_SPKMBCRAT_RATIO 0
441 #define FM_SPKMBCRAT_RATIO 0x1F
444 #define FB_SPKMBCATKL_TCATKL 0
445 #define FM_SPKMBCATKL_TCATKL 0xFF
448 #define FB_SPKMBCATKH_TCATKH 0
449 #define FM_SPKMBCATKH_TCATKH 0xFF
452 #define FB_SPKMBCRELL_TCRELL 0
453 #define FM_SPKMBCRELL_TCRELL 0xFF
456 #define FB_SPKMBCRELH_TCRELH 0
457 #define FM_SPKMBCRELH_TCRELH 0xFF
461 #define FM_DACMBCMUG_PHASE 0x20
463 #define FB_DACMBCMUG_MUGAIN 0
464 #define FM_DACMBCMUG_MUGAIN 0x1F
467 #define FB_DACMBCTHR_THRESH 0
468 #define FM_DACMBCTHR_THRESH 0xFF
471 #define FB_DACMBCRAT_RATIO 0
472 #define FM_DACMBCRAT_RATIO 0x1F
475 #define FB_DACMBCATKL_TCATKL 0
476 #define FM_DACMBCATKL_TCATKL 0xFF
479 #define FB_DACMBCATKH_TCATKH 0
480 #define FM_DACMBCATKH_TCATKH 0xFF
483 #define FB_DACMBCRELL_TCRELL 0
484 #define FM_DACMBCRELL_TCRELL 0xFF
487 #define FB_DACMBCRELH_TCRELH 0
488 #define FM_DACMBCRELH_TCRELH 0xFF
492 #define FM_SUBMBCMUG_PHASE 0x20
494 #define FB_SUBMBCMUG_MUGAIN 0
495 #define FM_SUBMBCMUG_MUGAIN 0x1F
498 #define FB_SUBMBCTHR_THRESH 0
499 #define FM_SUBMBCTHR_THRESH 0xFF
502 #define FB_SUBMBCRAT_RATIO 0
503 #define FM_SUBMBCRAT_RATIO 0x1F
506 #define FB_SUBMBCATKL_TCATKL 0
507 #define FM_SUBMBCATKL_TCATKL 0xFF
510 #define FB_SUBMBCATKH_TCATKH 0
511 #define FM_SUBMBCATKH_TCATKH 0xFF
514 #define FB_SUBMBCRELL_TCRELL 0
515 #define FM_SUBMBCRELL_TCRELL 0xFF
518 #define FB_SUBMBCRELH_TCRELH 0
519 #define FM_SUBMBCRELH_TCRELH 0xFF
522 #define FB_PAGESEL_PAGESEL 0
523 #define FM_PAGESEL_PAGESEL 0xFF
526 #define FB_RESET_RESET 0
527 #define FM_RESET_RESET 0xFF
528 #define FV_RESET_PWR_ON_DEFAULTS 0x85
532 #define FM_IRQEN_THRMINTEN 0x40
533 #define FV_THRMINTEN_ENABLED 0x40
534 #define FV_THRMINTEN_DISABLED 0x0
537 #define FM_IRQEN_HBPINTEN 0x20
538 #define FV_HBPINTEN_ENABLED 0x20
539 #define FV_HBPINTEN_DISABLED 0x0
542 #define FM_IRQEN_HSDINTEN 0x10
543 #define FV_HSDINTEN_ENABLED 0x10
544 #define FV_HSDINTEN_DISABLED 0x0
547 #define FM_IRQEN_HPDINTEN 0x8
548 #define FV_HPDINTEN_ENABLED 0x8
549 #define FV_HPDINTEN_DISABLED 0x0
552 #define FM_IRQEN_GPIO3INTEN 0x2
553 #define FV_GPIO3INTEN_ENABLED 0x2
554 #define FV_GPIO3INTEN_DISABLED 0x0
556 #define FB_IRQEN_GPIO2INTEN 0
557 #define FM_IRQEN_GPIO2INTEN 0x1
558 #define FV_GPIO2INTEN_ENABLED 0x1
559 #define FV_GPIO2INTEN_DISABLED 0x0
561 #define IRQEN_GPIOINTEN_ENABLED 0x1
562 #define IRQEN_GPIOINTEN_DISABLED 0x0
566 #define FM_IRQMASK_THRMIM 0x40
567 #define FV_THRMIM_MASKED 0x0
568 #define FV_THRMIM_NOT_MASKED 0x40
571 #define FM_IRQMASK_HBPIM 0x20
572 #define FV_HBPIM_MASKED 0x0
573 #define FV_HBPIM_NOT_MASKED 0x20
576 #define FM_IRQMASK_HSDIM 0x10
577 #define FV_HSDIM_MASKED 0x0
578 #define FV_HSDIM_NOT_MASKED 0x10
581 #define FM_IRQMASK_HPDIM 0x8
582 #define FV_HPDIM_MASKED 0x0
583 #define FV_HPDIM_NOT_MASKED 0x8
586 #define FM_IRQMASK_GPIO3M 0x2
587 #define FV_GPIO3M_MASKED 0x0
588 #define FV_GPIO3M_NOT_MASKED 0x2
590 #define FB_IRQMASK_GPIO2M 0
591 #define FM_IRQMASK_GPIO2M 0x1
592 #define FV_GPIO2M_MASKED 0x0
593 #define FV_GPIO2M_NOT_MASKED 0x1
595 #define IRQMASK_GPIOM_MASKED 0x0
596 #define IRQMASK_GPIOM_NOT_MASKED 0x1
600 #define FM_IRQSTAT_THRMINT 0x40
601 #define FV_THRMINT_INTERRUPTED 0x40
602 #define FV_THRMINT_NOT_INTERRUPTED 0x0
605 #define FM_IRQSTAT_HBPINT 0x20
606 #define FV_HBPINT_INTERRUPTED 0x20
607 #define FV_HBPINT_NOT_INTERRUPTED 0x0
610 #define FM_IRQSTAT_HSDINT 0x10
611 #define FV_HSDINT_INTERRUPTED 0x10
612 #define FV_HSDINT_NOT_INTERRUPTED 0x0
615 #define FM_IRQSTAT_HPDINT 0x8
616 #define FV_HPDINT_INTERRUPTED 0x8
617 #define FV_HPDINT_NOT_INTERRUPTED 0x0
620 #define FM_IRQSTAT_GPIO3INT 0x2
621 #define FV_GPIO3INT_INTERRUPTED 0x2
622 #define FV_GPIO3INT_NOT_INTERRUPTED 0x0
624 #define FB_IRQSTAT_GPIO2INT 0
625 #define FM_IRQSTAT_GPIO2INT 0x1
626 #define FV_GPIO2INT_INTERRUPTED 0x1
627 #define FV_GPIO2INT_NOT_INTERRUPTED 0x0
629 #define IRQSTAT_GPIOINT_INTERRUPTED 0x1
630 #define IRQSTAT_GPIOINT_NOT_INTERRUPTED 0x0
634 #define FM_DEVADD0_DEVADD0 0xFE
636 #define FB_DEVADD0_I2C_ADDRLK 0
637 #define FM_DEVADD0_I2C_ADDRLK 0x1
638 #define FV_I2C_ADDRLK_LOCK 0x1
641 #define FB_DEVID_DEV_ID 0
642 #define FM_DEVID_DEV_ID 0xFF
646 #define FM_DEVREV_MAJ_REV 0xF0
648 #define FB_DEVREV_MIN_REV 0
649 #define FM_DEVREV_MIN_REV 0xF
653 #define FM_PLLSTAT_PLL2LK 0x2
654 #define FV_PLL2LK_LOCKED 0x2
655 #define FV_PLL2LK_UNLOCKED 0x0
657 #define FB_PLLSTAT_PLL1LK 0
658 #define FM_PLLSTAT_PLL1LK 0x1
659 #define FV_PLL1LK_LOCKED 0x1
660 #define FV_PLL1LK_UNLOCKED 0x0
662 #define PLLSTAT_PLLLK_LOCKED 0x1
663 #define PLLSTAT_PLLLK_UNLOCKED 0x0
667 #define FM_PLLCTL_PU_PLL2 0x80
668 #define FV_PU_PLL2_PWR_UP 0x80
669 #define FV_PU_PLL2_PWR_DWN 0x0
672 #define FM_PLLCTL_PU_PLL1 0x40
673 #define FV_PU_PLL1_PWR_UP 0x40
674 #define FV_PU_PLL1_PWR_DWN 0x0
677 #define FM_PLLCTL_PLL2CLKEN 0x20
678 #define FV_PLL2CLKEN_ENABLE 0x20
679 #define FV_PLL2CLKEN_DISABLE 0x0
682 #define FM_PLLCTL_PLL1CLKEN 0x10
683 #define FV_PLL1CLKEN_ENABLE 0x10
684 #define FV_PLL1CLKEN_DISABLE 0x0
687 #define FM_PLLCTL_BCLKSEL 0xC
688 #define FV_BCLKSEL_BCLK1 0x0
689 #define FV_BCLKSEL_BCLK2 0x4
690 #define FV_BCLKSEL_BCLK3 0x8
692 #define FB_PLLCTL_PLLISEL 0
693 #define FM_PLLCTL_PLLISEL 0x3
694 #define FV_PLLISEL_XTAL 0x0
695 #define FV_PLLISEL_MCLK1 0x1
696 #define FV_PLLISEL_MCLK2 0x2
697 #define FV_PLLISEL_BCLK 0x3
699 #define PLLCTL_PU_PLL_PWR_UP 0x1
700 #define PLLCTL_PU_PLL_PWR_DWN 0x0
701 #define PLLCTL_PLLCLKEN_ENABLE 0x1
702 #define PLLCTL_PLLCLKEN_DISABLE 0x0
706 #define FM_ISRC_IBR 0x4
707 #define FV_IBR_44PT1 0x0
708 #define FV_IBR_48 0x4
710 #define FB_ISRC_IBM 0
711 #define FM_ISRC_IBM 0x3
712 #define FV_IBM_0PT25 0x0
713 #define FV_IBM_0PT5 0x1
714 #define FV_IBM_1 0x2
715 #define FV_IBM_2 0x3
719 #define FM_SCLKCTL_ASDM 0xC0
720 #define FV_ASDM_HALF 0x40
721 #define FV_ASDM_FULL 0x80
722 #define FV_ASDM_AUTO 0xC0
725 #define FM_SCLKCTL_DSDM 0x30
726 #define FV_DSDM_HALF 0x10
727 #define FV_DSDM_FULL 0x20
728 #define FV_DSDM_AUTO 0x30
731 #define FB_TIMEBASE_TIMEBASE 0
732 #define FM_TIMEBASE_TIMEBASE 0xFF
736 #define FM_I2SCMC_BCMP3 0x30
737 #define FV_BCMP3_AUTO 0x0
738 #define FV_BCMP3_32X 0x10
739 #define FV_BCMP3_40X 0x20
740 #define FV_BCMP3_64X 0x30
743 #define FM_I2SCMC_BCMP2 0xC
744 #define FV_BCMP2_AUTO 0x0
745 #define FV_BCMP2_32X 0x4
746 #define FV_BCMP2_40X 0x8
747 #define FV_BCMP2_64X 0xC
749 #define FB_I2SCMC_BCMP1 0
750 #define FM_I2SCMC_BCMP1 0x3
751 #define FV_BCMP1_AUTO 0x0
752 #define FV_BCMP1_32X 0x1
753 #define FV_BCMP1_40X 0x2
754 #define FV_BCMP1_64X 0x3
756 #define I2SCMC_BCMP_AUTO 0x0
757 #define I2SCMC_BCMP_32X 0x1
758 #define I2SCMC_BCMP_40X 0x2
759 #define I2SCMC_BCMP_64X 0x3
763 #define FM_MCLK2PINC_SLEWOUT 0xF0
766 #define FM_MCLK2PINC_MCLK2IO 0x4
767 #define FV_MCLK2IO_INPUT 0x0
768 #define FV_MCLK2IO_OUTPUT 0x4
770 #define FB_MCLK2PINC_MCLK2OS 0
771 #define FM_MCLK2PINC_MCLK2OS 0x3
772 #define FV_MCLK2OS_24PT576 0x0
773 #define FV_MCLK2OS_22PT5792 0x1
774 #define FV_MCLK2OS_PLL2 0x2
778 #define FM_I2SPINC0_SDO3TRI 0x80
781 #define FM_I2SPINC0_SDO2TRI 0x40
784 #define FM_I2SPINC0_SDO1TRI 0x20
787 #define FM_I2SPINC0_PCM3TRI 0x4
790 #define FM_I2SPINC0_PCM2TRI 0x2
792 #define FB_I2SPINC0_PCM1TRI 0
793 #define FM_I2SPINC0_PCM1TRI 0x1
797 #define FM_I2SPINC1_SDO3PDD 0x4
800 #define FM_I2SPINC1_SDO2PDD 0x2
802 #define FB_I2SPINC1_SDO1PDD 0
803 #define FM_I2SPINC1_SDO1PDD 0x1
807 #define FM_I2SPINC2_LR3PDD 0x20
810 #define FM_I2SPINC2_BC3PDD 0x10
813 #define FM_I2SPINC2_LR2PDD 0x8
816 #define FM_I2SPINC2_BC2PDD 0x4
819 #define FM_I2SPINC2_LR1PDD 0x2
821 #define FB_I2SPINC2_BC1PDD 0
822 #define FM_I2SPINC2_BC1PDD 0x1
826 #define FM_GPIOCTL0_GPIO3INTP 0x80
829 #define FM_GPIOCTL0_GPIO2INTP 0x40
832 #define FM_GPIOCTL0_GPIO3CFG 0x20
835 #define FM_GPIOCTL0_GPIO2CFG 0x10
838 #define FM_GPIOCTL0_GPIO3IO 0x8
841 #define FM_GPIOCTL0_GPIO2IO 0x4
844 #define FM_GPIOCTL0_GPIO1IO 0x2
846 #define FB_GPIOCTL0_GPIO0IO 0
847 #define FM_GPIOCTL0_GPIO0IO 0x1
851 #define FM_GPIOCTL1_GPIO3 0x80
854 #define FM_GPIOCTL1_GPIO2 0x40
857 #define FM_GPIOCTL1_GPIO1 0x20
860 #define FM_GPIOCTL1_GPIO0 0x10
863 #define FM_GPIOCTL1_GPIO3RD 0x8
866 #define FM_GPIOCTL1_GPIO2RD 0x4
869 #define FM_GPIOCTL1_GPIO1RD 0x2
871 #define FB_GPIOCTL1_GPIO0RD 0
872 #define FM_GPIOCTL1_GPIO0RD 0x1
876 #define FM_ASRC_ASRCOBW 0x80
879 #define FM_ASRC_ASRCIBW 0x40
882 #define FM_ASRC_ASRCOB 0x20
883 #define FV_ASRCOB_ACTIVE 0x0
884 #define FV_ASRCOB_BYPASSED 0x20
887 #define FM_ASRC_ASRCIB 0x10
888 #define FV_ASRCIB_ACTIVE 0x0
889 #define FV_ASRCIB_BYPASSED 0x10
892 #define FM_ASRC_ASRCOL 0x8
895 #define FM_ASRC_ASRCIL 0x4
899 #define FM_TDMCTL0_TDMMD 0x4
900 #define FV_TDMMD_200 0x0
901 #define FV_TDMMD_256 0x4
904 #define FM_TDMCTL0_SLSYNC 0x2
905 #define FV_SLSYNC_SHORT 0x0
906 #define FV_SLSYNC_LONG 0x2
908 #define FB_TDMCTL0_BDELAY 0
909 #define FM_TDMCTL0_BDELAY 0x1
910 #define FV_BDELAY_NO_DELAY 0x0
911 #define FV_BDELAY_1BCLK_DELAY 0x1
915 #define FM_TDMCTL1_TDMSO 0x60
916 #define FV_TDMSO_2 0x0
917 #define FV_TDMSO_4 0x20
918 #define FV_TDMSO_6 0x40
921 #define FM_TDMCTL1_TDMDSS 0x18
922 #define FV_TDMDSS_16 0x0
923 #define FV_TDMDSS_24 0x10
924 #define FV_TDMDSS_32 0x18
926 #define FB_TDMCTL1_TDMSI 0
927 #define FM_TDMCTL1_TDMSI 0x3
928 #define FV_TDMSI_2 0x0
929 #define FV_TDMSI_4 0x1
930 #define FV_TDMSI_6 0x2
934 #define FM_PWRM0_INPROC3PU 0x40
937 #define FM_PWRM0_INPROC2PU 0x20
940 #define FM_PWRM0_INPROC1PU 0x10
943 #define FM_PWRM0_INPROC0PU 0x8
946 #define FM_PWRM0_MICB2PU 0x4
949 #define FM_PWRM0_MICB1PU 0x2
951 #define FB_PWRM0_MCLKPEN 0
952 #define FM_PWRM0_MCLKPEN 0x1
956 #define FM_PWRM1_SUBPU 0x80
959 #define FM_PWRM1_HPLPU 0x40
962 #define FM_PWRM1_HPRPU 0x20
965 #define FM_PWRM1_SPKLPU 0x10
968 #define FM_PWRM1_SPKRPU 0x8
971 #define FM_PWRM1_D2S2PU 0x4
974 #define FM_PWRM1_D2S1PU 0x2
976 #define FB_PWRM1_VREFPU 0
977 #define FM_PWRM1_VREFPU 0x1
981 #define FM_PWRM2_I2S3OPU 0x20
982 #define FV_I2S3OPU_PWR_DOWN 0x0
983 #define FV_I2S3OPU_PWR_UP 0x20
986 #define FM_PWRM2_I2S2OPU 0x10
987 #define FV_I2S2OPU_PWR_DOWN 0x0
988 #define FV_I2S2OPU_PWR_UP 0x10
991 #define FM_PWRM2_I2S1OPU 0x8
992 #define FV_I2S1OPU_PWR_DOWN 0x0
993 #define FV_I2S1OPU_PWR_UP 0x8
996 #define FM_PWRM2_I2S3IPU 0x4
997 #define FV_I2S3IPU_PWR_DOWN 0x0
998 #define FV_I2S3IPU_PWR_UP 0x4
1001 #define FM_PWRM2_I2S2IPU 0x2
1002 #define FV_I2S2IPU_PWR_DOWN 0x0
1003 #define FV_I2S2IPU_PWR_UP 0x2
1005 #define FB_PWRM2_I2S1IPU 0
1006 #define FM_PWRM2_I2S1IPU 0x1
1007 #define FV_I2S1IPU_PWR_DOWN 0x0
1008 #define FV_I2S1IPU_PWR_UP 0x1
1010 #define PWRM2_I2SOPU_PWR_DOWN 0x0
1011 #define PWRM2_I2SOPU_PWR_UP 0x1
1012 #define PWRM2_I2SIPU_PWR_DOWN 0x0
1013 #define PWRM2_I2SIPU_PWR_UP 0x1
1017 #define FM_PWRM3_BGSBUP 0x40
1018 #define FV_BGSBUP_ON 0x0
1019 #define FV_BGSBUP_OFF 0x40
1022 #define FM_PWRM3_VGBAPU 0x20
1023 #define FV_VGBAPU_ON 0x0
1024 #define FV_VGBAPU_OFF 0x20
1027 #define FM_PWRM3_LLINEPU 0x10
1030 #define FM_PWRM3_RLINEPU 0x8
1034 #define FM_PWRM4_OPSUBPU 0x10
1037 #define FM_PWRM4_OPDACLPU 0x8
1040 #define FM_PWRM4_OPDACRPU 0x4
1043 #define FM_PWRM4_OPSPKLPU 0x2
1045 #define FB_PWRM4_OPSPKRPU 0
1046 #define FM_PWRM4_OPSPKRPU 0x1
1050 #define FM_I2SIDCTL_I2SI3DCTL 0x30
1053 #define FM_I2SIDCTL_I2SI2DCTL 0xC
1055 #define FB_I2SIDCTL_I2SI1DCTL 0
1056 #define FM_I2SIDCTL_I2SI1DCTL 0x3
1060 #define FM_I2SODCTL_I2SO3DCTL 0x30
1063 #define FM_I2SODCTL_I2SO2DCTL 0xC
1065 #define FB_I2SODCTL_I2SO1DCTL 0
1066 #define FM_I2SODCTL_I2SO1DCTL 0x3
1070 #define FM_AUDIOMUX1_ASRCIMUX 0xC0
1071 #define FV_ASRCIMUX_NONE 0x0
1072 #define FV_ASRCIMUX_I2S1 0x40
1073 #define FV_ASRCIMUX_I2S2 0x80
1074 #define FV_ASRCIMUX_I2S3 0xC0
1077 #define FM_AUDIOMUX1_I2S2MUX 0x38
1078 #define FV_I2S2MUX_I2S1 0x0
1079 #define FV_I2S2MUX_I2S2 0x8
1080 #define FV_I2S2MUX_I2S3 0x10
1081 #define FV_I2S2MUX_ADC_DMIC 0x18
1082 #define FV_I2S2MUX_DMIC2 0x20
1083 #define FV_I2S2MUX_CLASSD_DSP 0x28
1084 #define FV_I2S2MUX_DAC_DSP 0x30
1085 #define FV_I2S2MUX_SUB_DSP 0x38
1087 #define FB_AUDIOMUX1_I2S1MUX 0
1088 #define FM_AUDIOMUX1_I2S1MUX 0x7
1089 #define FV_I2S1MUX_I2S1 0x0
1090 #define FV_I2S1MUX_I2S2 0x1
1091 #define FV_I2S1MUX_I2S3 0x2
1092 #define FV_I2S1MUX_ADC_DMIC 0x3
1093 #define FV_I2S1MUX_DMIC2 0x4
1094 #define FV_I2S1MUX_CLASSD_DSP 0x5
1095 #define FV_I2S1MUX_DAC_DSP 0x6
1096 #define FV_I2S1MUX_SUB_DSP 0x7
1098 #define AUDIOMUX1_I2SMUX_I2S1 0x0
1099 #define AUDIOMUX1_I2SMUX_I2S2 0x1
1100 #define AUDIOMUX1_I2SMUX_I2S3 0x2
1101 #define AUDIOMUX1_I2SMUX_ADC_DMIC 0x3
1102 #define AUDIOMUX1_I2SMUX_DMIC2 0x4
1103 #define AUDIOMUX1_I2SMUX_CLASSD_DSP 0x5
1104 #define AUDIOMUX1_I2SMUX_DAC_DSP 0x6
1105 #define AUDIOMUX1_I2SMUX_SUB_DSP 0x7
1109 #define FM_AUDIOMUX2_ASRCOMUX 0xC0
1110 #define FV_ASRCOMUX_NONE 0x0
1111 #define FV_ASRCOMUX_I2S1 0x40
1112 #define FV_ASRCOMUX_I2S2 0x80
1113 #define FV_ASRCOMUX_I2S3 0xC0
1116 #define FM_AUDIOMUX2_DACMUX 0x38
1117 #define FV_DACMUX_I2S1 0x0
1118 #define FV_DACMUX_I2S2 0x8
1119 #define FV_DACMUX_I2S3 0x10
1120 #define FV_DACMUX_ADC_DMIC 0x18
1121 #define FV_DACMUX_DMIC2 0x20
1122 #define FV_DACMUX_CLASSD_DSP 0x28
1123 #define FV_DACMUX_DAC_DSP 0x30
1124 #define FV_DACMUX_SUB_DSP 0x38
1126 #define FB_AUDIOMUX2_I2S3MUX 0
1127 #define FM_AUDIOMUX2_I2S3MUX 0x7
1128 #define FV_I2S3MUX_I2S1 0x0
1129 #define FV_I2S3MUX_I2S2 0x1
1130 #define FV_I2S3MUX_I2S3 0x2
1131 #define FV_I2S3MUX_ADC_DMIC 0x3
1132 #define FV_I2S3MUX_DMIC2 0x4
1133 #define FV_I2S3MUX_CLASSD_DSP 0x5
1134 #define FV_I2S3MUX_DAC_DSP 0x6
1135 #define FV_I2S3MUX_SUB_DSP 0x7
1139 #define FM_AUDIOMUX3_SUBMUX 0xF8
1140 #define FV_SUBMUX_I2S1_L 0x0
1141 #define FV_SUBMUX_I2S1_R 0x8
1142 #define FV_SUBMUX_I2S1_LR 0x10
1143 #define FV_SUBMUX_I2S2_L 0x18
1144 #define FV_SUBMUX_I2S2_R 0x20
1145 #define FV_SUBMUX_I2S2_LR 0x28
1146 #define FV_SUBMUX_I2S3_L 0x30
1147 #define FV_SUBMUX_I2S3_R 0x38
1148 #define FV_SUBMUX_I2S3_LR 0x40
1149 #define FV_SUBMUX_ADC_DMIC_L 0x48
1150 #define FV_SUBMUX_ADC_DMIC_R 0x50
1151 #define FV_SUBMUX_ADC_DMIC_LR 0x58
1152 #define FV_SUBMUX_DMIC_L 0x60
1153 #define FV_SUBMUX_DMIC_R 0x68
1154 #define FV_SUBMUX_DMIC_LR 0x70
1155 #define FV_SUBMUX_CLASSD_DSP_L 0x78
1156 #define FV_SUBMUX_CLASSD_DSP_R 0x80
1157 #define FV_SUBMUX_CLASSD_DSP_LR 0x88
1159 #define FB_AUDIOMUX3_CLSSDMUX 0
1160 #define FM_AUDIOMUX3_CLSSDMUX 0x7
1161 #define FV_CLSSDMUX_I2S1 0x0
1162 #define FV_CLSSDMUX_I2S2 0x1
1163 #define FV_CLSSDMUX_I2S3 0x2
1164 #define FV_CLSSDMUX_ADC_DMIC 0x3
1165 #define FV_CLSSDMUX_DMIC2 0x4
1166 #define FV_CLSSDMUX_CLASSD_DSP 0x5
1167 #define FV_CLSSDMUX_DAC_DSP 0x6
1168 #define FV_CLSSDMUX_SUB_DSP 0x7
1172 #define FM_HSDCTL1_HPJKTYPE 0x80
1175 #define FM_HSDCTL1_CON_DET_PWD 0x40
1178 #define FM_HSDCTL1_DETCYC 0x30
1181 #define FM_HSDCTL1_HPDLYBYP 0x8
1184 #define FM_HSDCTL1_HSDETPOL 0x4
1187 #define FM_HSDCTL1_HPID_EN 0x2
1189 #define FB_HSDCTL1_GBLHS_EN 0
1190 #define FM_HSDCTL1_GBLHS_EN 0x1
1194 #define FM_HSDCTL2_FMICBIAS1 0xC0
1197 #define FM_HSDCTL2_MB1MODE 0x20
1198 #define FV_MB1MODE_AUTO 0x0
1199 #define FV_MB1MODE_MANUAL 0x20
1202 #define FM_HSDCTL2_FORCETRG 0x10
1205 #define FM_HSDCTL2_SWMODE 0x8
1208 #define FM_HSDCTL2_GHSHIZ 0x4
1210 #define FB_HSDCTL2_FPLUGTYPE 0
1211 #define FM_HSDCTL2_FPLUGTYPE 0x3
1215 #define FM_HSDSTAT_MBIAS1DRV 0x60
1218 #define FM_HSDSTAT_HSDETSTAT 0x8
1221 #define FM_HSDSTAT_PLUGTYPE 0x6
1223 #define FB_HSDSTAT_HSDETDONE 0
1224 #define FM_HSDSTAT_HSDETDONE 0x1
1227 #define FB_HSDDELAY_T_STABLE 0
1228 #define FM_HSDDELAY_T_STABLE 0x7
1232 #define FM_BUTCTL_BPUSHSTAT 0x80
1235 #define FM_BUTCTL_BPUSHDET 0x40
1238 #define FM_BUTCTL_BPUSHEN 0x20
1241 #define FM_BUTCTL_BSTABLE_L 0x18
1243 #define FB_BUTCTL_BSTABLE_S 0
1244 #define FM_BUTCTL_BSTABLE_S 0x7
1248 #define FM_CH0AIC_INSELL 0xC0
1251 #define FM_CH0AIC_MICBST0 0x30
1254 #define FM_CH0AIC_LADCIN 0xC
1257 #define FM_CH0AIC_IN_BYPS_L_SEL 0x2
1259 #define FB_CH0AIC_IPCH0S 0
1260 #define FM_CH0AIC_IPCH0S 0x1
1264 #define FM_CH1AIC_INSELR 0xC0
1267 #define FM_CH1AIC_MICBST1 0x30
1270 #define FM_CH1AIC_RADCIN 0xC
1273 #define FM_CH1AIC_IN_BYPS_R_SEL 0x2
1275 #define FB_CH1AIC_IPCH1S 0
1276 #define FM_CH1AIC_IPCH1S 0x1
1280 #define FM_ICTL0_IN1POL 0x80
1283 #define FM_ICTL0_IN0POL 0x40
1286 #define FM_ICTL0_INPCH10SEL 0x30
1289 #define FM_ICTL0_IN1MUTE 0x8
1292 #define FM_ICTL0_IN0MUTE 0x4
1295 #define FM_ICTL0_IN1HP 0x2
1297 #define FB_ICTL0_IN0HP 0
1298 #define FM_ICTL0_IN0HP 0x1
1302 #define FM_ICTL1_IN3POL 0x80
1305 #define FM_ICTL1_IN2POL 0x40
1308 #define FM_ICTL1_INPCH32SEL 0x30
1311 #define FM_ICTL1_IN3MUTE 0x8
1314 #define FM_ICTL1_IN2MUTE 0x4
1317 #define FM_ICTL1_IN3HP 0x2
1319 #define FB_ICTL1_IN2HP 0
1320 #define FM_ICTL1_IN2HP 0x1
1324 #define FM_MICBIAS_MICBOV2 0x30
1327 #define FM_MICBIAS_MICBOV1 0xC0
1330 #define FM_MICBIAS_SPARE1 0xC
1332 #define FB_MICBIAS_SPARE2 0
1333 #define FM_MICBIAS_SPARE2 0x3
1337 #define FM_PGAZ_INHPOR 0x2
1339 #define FB_PGAZ_TOEN 0
1340 #define FM_PGAZ_TOEN 0x1
1343 #define FB_ASRCILVOL_ASRCILVOL 0
1344 #define FM_ASRCILVOL_ASRCILVOL 0xFF
1347 #define FB_ASRCIRVOL_ASRCIRVOL 0
1348 #define FM_ASRCIRVOL_ASRCIRVOL 0xFF
1351 #define FB_ASRCOLVOL_ASRCOLVOL 0
1352 #define FM_ASRCOLVOL_ASRCOLVOL 0xFF
1355 #define FB_ASRCORVOL_ASRCOLVOL 0
1356 #define FM_ASRCORVOL_ASRCOLVOL 0xFF
1360 #define FM_IVOLCTLU_IFADE 0x8
1363 #define FM_IVOLCTLU_INPVOLU 0x4
1366 #define FM_IVOLCTLU_PGAVOLU 0x2
1368 #define FB_IVOLCTLU_ASRCVOLU 0
1369 #define FM_IVOLCTLU_ASRCVOLU 0x1
1373 #define FM_ALCCTL0_ALCMODE 0x80
1376 #define FM_ALCCTL0_ALCREF 0x70
1379 #define FM_ALCCTL0_ALCEN3 0x8
1382 #define FM_ALCCTL0_ALCEN2 0x4
1385 #define FM_ALCCTL0_ALCEN1 0x2
1387 #define FB_ALCCTL0_ALCEN0 0
1388 #define FM_ALCCTL0_ALCEN0 0x1
1392 #define FM_ALCCTL1_MAXGAIN 0x70
1394 #define FB_ALCCTL1_ALCL 0
1395 #define FM_ALCCTL1_ALCL 0xF
1399 #define FM_ALCCTL2_ALCZC 0x80
1402 #define FM_ALCCTL2_MINGAIN 0x70
1404 #define FB_ALCCTL2_HLD 0
1405 #define FM_ALCCTL2_HLD 0xF
1409 #define FM_ALCCTL3_DCY 0xF0
1411 #define FB_ALCCTL3_ATK 0
1412 #define FM_ALCCTL3_ATK 0xF
1416 #define FM_NGATE_NGTH 0xF8
1419 #define FM_NGATE_NGG 0x6
1421 #define FB_NGATE_NGAT 0
1422 #define FM_NGATE_NGAT 0x1
1426 #define FM_DMICCTL_DMIC2EN 0x80
1429 #define FM_DMICCTL_DMIC1EN 0x40
1432 #define FM_DMICCTL_DMONO 0x10
1435 #define FM_DMICCTL_DMDCLK 0xC
1437 #define FB_DMICCTL_DMRATE 0
1438 #define FM_DMICCTL_DMRATE 0x3
1442 #define FM_DACCTL_DACPOLR 0x80
1443 #define FV_DACPOLR_NORMAL 0x0
1444 #define FV_DACPOLR_INVERTED 0x80
1447 #define FM_DACCTL_DACPOLL 0x40
1448 #define FV_DACPOLL_NORMAL 0x0
1449 #define FV_DACPOLL_INVERTED 0x40
1452 #define FM_DACCTL_DACDITH 0x30
1453 #define FV_DACDITH_DYNAMIC_HALF 0x0
1454 #define FV_DACDITH_DYNAMIC_FULL 0x10
1455 #define FV_DACDITH_DISABLED 0x20
1456 #define FV_DACDITH_STATIC 0x30
1459 #define FM_DACCTL_DACMUTE 0x8
1460 #define FV_DACMUTE_ENABLE 0x8
1461 #define FV_DACMUTE_DISABLE 0x0
1464 #define FM_DACCTL_DACDEM 0x4
1465 #define FV_DACDEM_ENABLE 0x4
1466 #define FV_DACDEM_DISABLE 0x0
1468 #define FB_DACCTL_ABYPASS 0
1469 #define FM_DACCTL_ABYPASS 0x1
1473 #define FM_SPKCTL_SPKPOLR 0x80
1474 #define FV_SPKPOLR_NORMAL 0x0
1475 #define FV_SPKPOLR_INVERTED 0x80
1478 #define FM_SPKCTL_SPKPOLL 0x40
1479 #define FV_SPKPOLL_NORMAL 0x0
1480 #define FV_SPKPOLL_INVERTED 0x40
1483 #define FM_SPKCTL_SPKMUTE 0x8
1484 #define FV_SPKMUTE_ENABLE 0x8
1485 #define FV_SPKMUTE_DISABLE 0x0
1488 #define FM_SPKCTL_SPKDEM 0x4
1489 #define FV_SPKDEM_ENABLE 0x4
1490 #define FV_SPKDEM_DISABLE 0x0
1494 #define FM_SUBCTL_SUBPOL 0x80
1497 #define FM_SUBCTL_SUBMUTE 0x8
1500 #define FM_SUBCTL_SUBDEM 0x4
1503 #define FM_SUBCTL_SUBMUX 0x2
1505 #define FB_SUBCTL_SUBILMDIS 0
1506 #define FM_SUBCTL_SUBILMDIS 0x1
1510 #define FM_DCCTL_SUBDCBYP 0x80
1513 #define FM_DCCTL_DACDCBYP 0x40
1516 #define FM_DCCTL_SPKDCBYP 0x20
1518 #define FB_DCCTL_DCCOEFSEL 0
1519 #define FM_DCCTL_DCCOEFSEL 0x7
1523 #define FM_OVOLCTLU_OFADE 0x10
1526 #define FM_OVOLCTLU_SUBVOLU 0x8
1529 #define FM_OVOLCTLU_MVOLU 0x4
1532 #define FM_OVOLCTLU_SPKVOLU 0x2
1534 #define FB_OVOLCTLU_HPVOLU 0
1535 #define FM_OVOLCTLU_HPVOLU 0x1
1539 #define FM_MUTEC_ZDSTAT 0x80
1542 #define FM_MUTEC_ZDLEN 0x30
1545 #define FM_MUTEC_APWD 0x8
1548 #define FM_MUTEC_AMUTE 0x4
1551 #define FB_MVOLL_MVOL_L 0
1552 #define FM_MVOLL_MVOL_L 0xFF
1555 #define FB_MVOLR_MVOL_R 0
1556 #define FM_MVOLR_MVOL_R 0xFF
1559 #define FB_HPVOLL_HPVOL_L 0
1560 #define FM_HPVOLL_HPVOL_L 0x7F
1563 #define FB_HPVOLR_HPVOL_R 0
1564 #define FM_HPVOLR_HPVOL_R 0x7F
1567 #define FB_SPKVOLL_SPKVOL_L 0
1568 #define FM_SPKVOLL_SPKVOL_L 0x7F
1571 #define FB_SPKVOLR_SPKVOL_R 0
1572 #define FM_SPKVOLR_SPKVOL_R 0x7F
1575 #define FB_SUBVOL_SUBVOL 0
1576 #define FM_SUBVOL_SUBVOL 0x7F
1580 #define FM_COP0_COPATTEN 0x80
1583 #define FM_COP0_COPGAIN 0x40
1586 #define FM_COP0_HDELTAEN 0x20
1588 #define FB_COP0_COPTARGET 0
1589 #define FM_COP0_COPTARGET 0x1F
1593 #define FM_COP1_HDCOMPMODE 0x40
1596 #define FM_COP1_AVGLENGTH 0x3C
1598 #define FB_COP1_MONRATE 0
1599 #define FM_COP1_MONRATE 0x3
1603 #define FM_COPSTAT_HDELTADET 0x80
1606 #define FM_COPSTAT_UV 0x40
1608 #define FB_COPSTAT_COPADJ 0
1609 #define FM_COPSTAT_COPADJ 0x3F
1613 #define FM_PWM0_SCTO 0xC0
1616 #define FM_PWM0_UVLO 0x20
1619 #define FM_PWM0_BFDIS 0x8
1622 #define FM_PWM0_PWMMODE 0x4
1624 #define FB_PWM0_NOOFFSET 0
1625 #define FM_PWM0_NOOFFSET 0x1
1629 #define FM_PWM1_DITHPOS 0x70
1632 #define FM_PWM1_DYNDITH 0x2
1634 #define FB_PWM1_DITHDIS 0
1635 #define FM_PWM1_DITHDIS 0x1
1640 #define FM_PWM3_PWMMUX 0xC0
1642 #define FB_PWM3_CVALUE 0
1643 #define FM_PWM3_CVALUE 0x7
1647 #define FM_HPSW_HPDETSTATE 0x10
1650 #define FM_HPSW_HPSWEN 0xC
1653 #define FM_HPSW_HPSWPOL 0x2
1655 #define FB_HPSW_TSDEN 0
1656 #define FM_HPSW_TSDEN 0x1
1660 #define FM_THERMTS_TRIPHS 0x80
1663 #define FM_THERMTS_TRIPLS 0x40
1666 #define FM_THERMTS_TRIPSPLIT 0x30
1669 #define FM_THERMTS_TRIPSHIFT 0xC
1671 #define FB_THERMTS_TSPOLL 0
1672 #define FM_THERMTS_TSPOLL 0x3
1676 #define FM_THERMSPK1_FORCEPWD 0x80
1679 #define FM_THERMSPK1_INSTCUTMODE 0x40
1682 #define FM_THERMSPK1_INCRATIO 0x30
1685 #define FM_THERMSPK1_INCSTEP 0xC
1687 #define FB_THERMSPK1_DECSTEP 0
1688 #define FM_THERMSPK1_DECSTEP 0x3
1692 #define FM_THERMSTAT_FPWDS 0x80
1694 #define FB_THERMSTAT_VOLSTAT 0
1695 #define FM_THERMSTAT_VOLSTAT 0x7F
1699 #define FM_SCSTAT_ESDF 0x18
1702 #define FM_SCSTAT_CPF 0x4
1704 #define FB_SCSTAT_CLSDF 0
1705 #define FM_SCSTAT_CLSDF 0x3
1709 #define FM_SDMON_SDFORCE 0x80
1711 #define FB_SDMON_SDVALUE 0
1712 #define FM_SDMON_SDVALUE 0x1F
1716 #define FM_SPKEQFILT_EQ2EN 0x80
1717 #define FV_EQ2EN_ENABLE 0x80
1718 #define FV_EQ2EN_DISABLE 0x0
1721 #define FM_SPKEQFILT_EQ2BE 0x70
1724 #define FM_SPKEQFILT_EQ1EN 0x8
1725 #define FV_EQ1EN_ENABLE 0x8
1726 #define FV_EQ1EN_DISABLE 0x0
1728 #define FB_SPKEQFILT_EQ1BE 0
1729 #define FM_SPKEQFILT_EQ1BE 0x7
1731 #define SPKEQFILT_EQEN_ENABLE 0x1
1732 #define SPKEQFILT_EQEN_DISABLE 0x0
1735 #define FB_SPKCRWDL_WDATA_L 0
1736 #define FM_SPKCRWDL_WDATA_L 0xFF
1739 #define FB_SPKCRWDM_WDATA_M 0
1740 #define FM_SPKCRWDM_WDATA_M 0xFF
1743 #define FB_SPKCRWDH_WDATA_H 0
1744 #define FM_SPKCRWDH_WDATA_H 0xFF
1747 #define FB_SPKCRRDL_RDATA_L 0
1748 #define FM_SPKCRRDL_RDATA_L 0xFF
1751 #define FB_SPKCRRDM_RDATA_M 0
1752 #define FM_SPKCRRDM_RDATA_M 0xFF
1755 #define FB_SPKCRRDH_RDATA_H 0
1756 #define FM_SPKCRRDH_RDATA_H 0xFF
1759 #define FB_SPKCRADD_ADDRESS 0
1760 #define FM_SPKCRADD_ADDRESS 0xFF
1764 #define FM_SPKCRS_ACCSTAT 0x80
1768 #define FM_SPKMBCEN_MBCEN3 0x4
1769 #define FV_MBCEN3_ENABLE 0x4
1770 #define FV_MBCEN3_DISABLE 0x0
1773 #define FM_SPKMBCEN_MBCEN2 0x2
1774 #define FV_MBCEN2_ENABLE 0x2
1775 #define FV_MBCEN2_DISABLE 0x0
1777 #define FB_SPKMBCEN_MBCEN1 0
1778 #define FM_SPKMBCEN_MBCEN1 0x1
1779 #define FV_MBCEN1_ENABLE 0x1
1780 #define FV_MBCEN1_DISABLE 0x0
1782 #define SPKMBCEN_MBCEN_ENABLE 0x1
1783 #define SPKMBCEN_MBCEN_DISABLE 0x0
1787 #define FM_SPKMBCCTL_LVLMODE3 0x20
1790 #define FM_SPKMBCCTL_WINSEL3 0x10
1793 #define FM_SPKMBCCTL_LVLMODE2 0x8
1796 #define FM_SPKMBCCTL_WINSEL2 0x4
1799 #define FM_SPKMBCCTL_LVLMODE1 0x2
1801 #define FB_SPKMBCCTL_WINSEL1 0
1802 #define FM_SPKMBCCTL_WINSEL1 0x1
1806 #define FM_SPKCLECTL_LVLMODE 0x10
1809 #define FM_SPKCLECTL_WINSEL 0x8
1812 #define FM_SPKCLECTL_EXPEN 0x4
1813 #define FV_EXPEN_ENABLE 0x4
1814 #define FV_EXPEN_DISABLE 0x0
1817 #define FM_SPKCLECTL_LIMEN 0x2
1818 #define FV_LIMEN_ENABLE 0x2
1819 #define FV_LIMEN_DISABLE 0x0
1821 #define FB_SPKCLECTL_COMPEN 0
1822 #define FM_SPKCLECTL_COMPEN 0x1
1823 #define FV_COMPEN_ENABLE 0x1
1824 #define FV_COMPEN_DISABLE 0x0
1827 #define FB_SPKCLEMUG_MUGAIN 0
1828 #define FM_SPKCLEMUG_MUGAIN 0x1F
1831 #define FB_SPKCOMPTHR_THRESH 0
1832 #define FM_SPKCOMPTHR_THRESH 0xFF
1835 #define FB_SPKCOMPRAT_RATIO 0
1836 #define FM_SPKCOMPRAT_RATIO 0x1F
1839 #define FB_SPKCOMPATKL_TCATKL 0
1840 #define FM_SPKCOMPATKL_TCATKL 0xFF
1843 #define FB_SPKCOMPATKH_TCATKH 0
1844 #define FM_SPKCOMPATKH_TCATKH 0xFF
1847 #define FB_SPKCOMPRELL_TCRELL 0
1848 #define FM_SPKCOMPRELL_TCRELL 0xFF
1851 #define FB_SPKCOMPRELH_TCRELH 0
1852 #define FM_SPKCOMPRELH_TCRELH 0xFF
1855 #define FB_SPKLIMTHR_THRESH 0
1856 #define FM_SPKLIMTHR_THRESH 0xFF
1859 #define FB_SPKLIMTGT_TARGET 0
1860 #define FM_SPKLIMTGT_TARGET 0xFF
1863 #define FB_SPKLIMATKL_TCATKL 0
1864 #define FM_SPKLIMATKL_TCATKL 0xFF
1867 #define FB_SPKLIMATKH_TCATKH 0
1868 #define FM_SPKLIMATKH_TCATKH 0xFF
1871 #define FB_SPKLIMRELL_TCRELL 0
1872 #define FM_SPKLIMRELL_TCRELL 0xFF
1875 #define FB_SPKLIMRELH_TCRELH 0
1876 #define FM_SPKLIMRELH_TCRELH 0xFF
1879 #define FB_SPKEXPTHR_THRESH 0
1880 #define FM_SPKEXPTHR_THRESH 0xFF
1883 #define FB_SPKEXPRAT_RATIO 0
1884 #define FM_SPKEXPRAT_RATIO 0x7
1887 #define FB_SPKEXPATKL_TCATKL 0
1888 #define FM_SPKEXPATKL_TCATKL 0xFF
1891 #define FB_SPKEXPATKH_TCATKH 0
1892 #define FM_SPKEXPATKH_TCATKH 0xFF
1895 #define FB_SPKEXPRELL_TCRELL 0
1896 #define FM_SPKEXPRELL_TCRELL 0xFF
1899 #define FB_SPKEXPRELH_TCRELH 0
1900 #define FM_SPKEXPRELH_TCRELH 0xFF
1904 #define FM_SPKFXCTL_3DEN 0x10
1907 #define FM_SPKFXCTL_TEEN 0x8
1910 #define FM_SPKFXCTL_TNLFBYP 0x4
1913 #define FM_SPKFXCTL_BEEN 0x2
1915 #define FB_SPKFXCTL_BNLFBYP 0
1916 #define FM_SPKFXCTL_BNLFBYP 0x1
1920 #define FM_DACEQFILT_EQ2EN 0x80
1921 #define FV_EQ2EN_ENABLE 0x80
1922 #define FV_EQ2EN_DISABLE 0x0
1925 #define FM_DACEQFILT_EQ2BE 0x70
1928 #define FM_DACEQFILT_EQ1EN 0x8
1929 #define FV_EQ1EN_ENABLE 0x8
1930 #define FV_EQ1EN_DISABLE 0x0
1932 #define FB_DACEQFILT_EQ1BE 0
1933 #define FM_DACEQFILT_EQ1BE 0x7
1935 #define DACEQFILT_EQEN_ENABLE 0x1
1936 #define DACEQFILT_EQEN_DISABLE 0x0
1939 #define FB_DACCRWDL_WDATA_L 0
1940 #define FM_DACCRWDL_WDATA_L 0xFF
1943 #define FB_DACCRWDM_WDATA_M 0
1944 #define FM_DACCRWDM_WDATA_M 0xFF
1947 #define FB_DACCRWDH_WDATA_H 0
1948 #define FM_DACCRWDH_WDATA_H 0xFF
1951 #define FB_DACCRRDL_RDATA_L 0
1952 #define FM_DACCRRDL_RDATA_L 0xFF
1955 #define FB_DACCRRDM_RDATA_M 0
1956 #define FM_DACCRRDM_RDATA_M 0xFF
1959 #define FB_DACCRRDH_RDATA_H 0
1960 #define FM_DACCRRDH_RDATA_H 0xFF
1963 #define FB_DACCRADD_ADDRESS 0
1964 #define FM_DACCRADD_ADDRESS 0xFF
1968 #define FM_DACCRS_ACCSTAT 0x80
1972 #define FM_DACMBCEN_MBCEN3 0x4
1973 #define FV_MBCEN3_ENABLE 0x4
1974 #define FV_MBCEN3_DISABLE 0x0
1977 #define FM_DACMBCEN_MBCEN2 0x2
1978 #define FV_MBCEN2_ENABLE 0x2
1979 #define FV_MBCEN2_DISABLE 0x0
1981 #define FB_DACMBCEN_MBCEN1 0
1982 #define FM_DACMBCEN_MBCEN1 0x1
1983 #define FV_MBCEN1_ENABLE 0x1
1984 #define FV_MBCEN1_DISABLE 0x0
1986 #define DACMBCEN_MBCEN_ENABLE 0x1
1987 #define DACMBCEN_MBCEN_DISABLE 0x0
1991 #define FM_DACMBCCTL_LVLMODE3 0x20
1994 #define FM_DACMBCCTL_WINSEL3 0x10
1997 #define FM_DACMBCCTL_LVLMODE2 0x8
2000 #define FM_DACMBCCTL_WINSEL2 0x4
2003 #define FM_DACMBCCTL_LVLMODE1 0x2
2005 #define FB_DACMBCCTL_WINSEL1 0
2006 #define FM_DACMBCCTL_WINSEL1 0x1
2010 #define FM_DACCLECTL_LVLMODE 0x10
2013 #define FM_DACCLECTL_WINSEL 0x8
2016 #define FM_DACCLECTL_EXPEN 0x4
2017 #define FV_EXPEN_ENABLE 0x4
2018 #define FV_EXPEN_DISABLE 0x0
2021 #define FM_DACCLECTL_LIMEN 0x2
2022 #define FV_LIMEN_ENABLE 0x2
2023 #define FV_LIMEN_DISABLE 0x0
2025 #define FB_DACCLECTL_COMPEN 0
2026 #define FM_DACCLECTL_COMPEN 0x1
2027 #define FV_COMPEN_ENABLE 0x1
2028 #define FV_COMPEN_DISABLE 0x0
2031 #define FB_DACCLEMUG_MUGAIN 0
2032 #define FM_DACCLEMUG_MUGAIN 0x1F
2035 #define FB_DACCOMPTHR_THRESH 0
2036 #define FM_DACCOMPTHR_THRESH 0xFF
2039 #define FB_DACCOMPRAT_RATIO 0
2040 #define FM_DACCOMPRAT_RATIO 0x1F
2043 #define FB_DACCOMPATKL_TCATKL 0
2044 #define FM_DACCOMPATKL_TCATKL 0xFF
2047 #define FB_DACCOMPATKH_TCATKH 0
2048 #define FM_DACCOMPATKH_TCATKH 0xFF
2051 #define FB_DACCOMPRELL_TCRELL 0
2052 #define FM_DACCOMPRELL_TCRELL 0xFF
2055 #define FB_DACCOMPRELH_TCRELH 0
2056 #define FM_DACCOMPRELH_TCRELH 0xFF
2059 #define FB_DACLIMTHR_THRESH 0
2060 #define FM_DACLIMTHR_THRESH 0xFF
2063 #define FB_DACLIMTGT_TARGET 0
2064 #define FM_DACLIMTGT_TARGET 0xFF
2067 #define FB_DACLIMATKL_TCATKL 0
2068 #define FM_DACLIMATKL_TCATKL 0xFF
2071 #define FB_DACLIMATKH_TCATKH 0
2072 #define FM_DACLIMATKH_TCATKH 0xFF
2075 #define FB_DACLIMRELL_TCRELL 0
2076 #define FM_DACLIMRELL_TCRELL 0xFF
2079 #define FB_DACLIMRELH_TCRELH 0
2080 #define FM_DACLIMRELH_TCRELH 0xFF
2083 #define FB_DACEXPTHR_THRESH 0
2084 #define FM_DACEXPTHR_THRESH 0xFF
2087 #define FB_DACEXPRAT_RATIO 0
2088 #define FM_DACEXPRAT_RATIO 0x7
2091 #define FB_DACEXPATKL_TCATKL 0
2092 #define FM_DACEXPATKL_TCATKL 0xFF
2095 #define FB_DACEXPATKH_TCATKH 0
2096 #define FM_DACEXPATKH_TCATKH 0xFF
2099 #define FB_DACEXPRELL_TCRELL 0
2100 #define FM_DACEXPRELL_TCRELL 0xFF
2103 #define FB_DACEXPRELH_TCRELH 0
2104 #define FM_DACEXPRELH_TCRELH 0xFF
2108 #define FM_DACFXCTL_3DEN 0x10
2111 #define FM_DACFXCTL_TEEN 0x8
2114 #define FM_DACFXCTL_TNLFBYP 0x4
2117 #define FM_DACFXCTL_BEEN 0x2
2119 #define FB_DACFXCTL_BNLFBYP 0
2120 #define FM_DACFXCTL_BNLFBYP 0x1
2124 #define FM_SUBEQFILT_EQ2EN 0x80
2125 #define FV_EQ2EN_ENABLE 0x80
2126 #define FV_EQ2EN_DISABLE 0x0
2129 #define FM_SUBEQFILT_EQ2BE 0x70
2132 #define FM_SUBEQFILT_EQ1EN 0x8
2133 #define FV_EQ1EN_ENABLE 0x8
2134 #define FV_EQ1EN_DISABLE 0x0
2136 #define FB_SUBEQFILT_EQ1BE 0
2137 #define FM_SUBEQFILT_EQ1BE 0x7
2139 #define SUBEQFILT_EQEN_ENABLE 0x1
2140 #define SUBEQFILT_EQEN_DISABLE 0x0
2143 #define FB_SUBCRWDL_WDATA_L 0
2144 #define FM_SUBCRWDL_WDATA_L 0xFF
2147 #define FB_SUBCRWDM_WDATA_M 0
2148 #define FM_SUBCRWDM_WDATA_M 0xFF
2151 #define FB_SUBCRWDH_WDATA_H 0
2152 #define FM_SUBCRWDH_WDATA_H 0xFF
2155 #define FB_SUBCRRDL_RDATA_L 0
2156 #define FM_SUBCRRDL_RDATA_L 0xFF
2159 #define FB_SUBCRRDM_RDATA_M 0
2160 #define FM_SUBCRRDM_RDATA_M 0xFF
2163 #define FB_SUBCRRDH_RDATA_H 0
2164 #define FM_SUBCRRDH_RDATA_H 0xFF
2167 #define FB_SUBCRADD_ADDRESS 0
2168 #define FM_SUBCRADD_ADDRESS 0xFF
2172 #define FM_SUBCRS_ACCSTAT 0x80
2176 #define FM_SUBMBCEN_MBCEN3 0x4
2177 #define FV_MBCEN3_ENABLE 0x4
2178 #define FV_MBCEN3_DISABLE 0x0
2181 #define FM_SUBMBCEN_MBCEN2 0x2
2182 #define FV_MBCEN2_ENABLE 0x2
2183 #define FV_MBCEN2_DISABLE 0x0
2185 #define FB_SUBMBCEN_MBCEN1 0
2186 #define FM_SUBMBCEN_MBCEN1 0x1
2187 #define FV_MBCEN1_ENABLE 0x1
2188 #define FV_MBCEN1_DISABLE 0x0
2190 #define SUBMBCEN_MBCEN_ENABLE 0x1
2191 #define SUBMBCEN_MBCEN_DISABLE 0x0
2195 #define FM_SUBMBCCTL_LVLMODE3 0x20
2198 #define FM_SUBMBCCTL_WINSEL3 0x10
2201 #define FM_SUBMBCCTL_LVLMODE2 0x8
2204 #define FM_SUBMBCCTL_WINSEL2 0x4
2207 #define FM_SUBMBCCTL_LVLMODE1 0x2
2209 #define FB_SUBMBCCTL_WINSEL1 0
2210 #define FM_SUBMBCCTL_WINSEL1 0x1
2214 #define FM_SUBCLECTL_LVLMODE 0x10
2217 #define FM_SUBCLECTL_WINSEL 0x8
2220 #define FM_SUBCLECTL_EXPEN 0x4
2221 #define FV_EXPEN_ENABLE 0x4
2222 #define FV_EXPEN_DISABLE 0x0
2225 #define FM_SUBCLECTL_LIMEN 0x2
2226 #define FV_LIMEN_ENABLE 0x2
2227 #define FV_LIMEN_DISABLE 0x0
2229 #define FB_SUBCLECTL_COMPEN 0
2230 #define FM_SUBCLECTL_COMPEN 0x1
2231 #define FV_COMPEN_ENABLE 0x1
2232 #define FV_COMPEN_DISABLE 0x0
2235 #define FB_SUBCLEMUG_MUGAIN 0
2236 #define FM_SUBCLEMUG_MUGAIN 0x1F
2239 #define FB_SUBCOMPTHR_THRESH 0
2240 #define FM_SUBCOMPTHR_THRESH 0xFF
2243 #define FB_SUBCOMPRAT_RATIO 0
2244 #define FM_SUBCOMPRAT_RATIO 0x1F
2247 #define FB_SUBCOMPATKL_TCATKL 0
2248 #define FM_SUBCOMPATKL_TCATKL 0xFF
2251 #define FB_SUBCOMPATKH_TCATKH 0
2252 #define FM_SUBCOMPATKH_TCATKH 0xFF
2255 #define FB_SUBCOMPRELL_TCRELL 0
2256 #define FM_SUBCOMPRELL_TCRELL 0xFF
2259 #define FB_SUBCOMPRELH_TCRELH 0
2260 #define FM_SUBCOMPRELH_TCRELH 0xFF
2263 #define FB_SUBLIMTHR_THRESH 0
2264 #define FM_SUBLIMTHR_THRESH 0xFF
2267 #define FB_SUBLIMTGT_TARGET 0
2268 #define FM_SUBLIMTGT_TARGET 0xFF
2271 #define FB_SUBLIMATKL_TCATKL 0
2272 #define FM_SUBLIMATKL_TCATKL 0xFF
2275 #define FB_SUBLIMATKH_TCATKH 0
2276 #define FM_SUBLIMATKH_TCATKH 0xFF
2279 #define FB_SUBLIMRELL_TCRELL 0
2280 #define FM_SUBLIMRELL_TCRELL 0xFF
2283 #define FB_SUBLIMRELH_TCRELH 0
2284 #define FM_SUBLIMRELH_TCRELH 0xFF
2287 #define FB_SUBEXPTHR_THRESH 0
2288 #define FM_SUBEXPTHR_THRESH 0xFF
2291 #define FB_SUBEXPRAT_RATIO 0
2292 #define FM_SUBEXPRAT_RATIO 0x7
2295 #define FB_SUBEXPATKL_TCATKL 0
2296 #define FM_SUBEXPATKL_TCATKL 0xFF
2299 #define FB_SUBEXPATKH_TCATKH 0
2300 #define FM_SUBEXPATKH_TCATKH 0xFF
2303 #define FB_SUBEXPRELL_TCRELL 0
2304 #define FM_SUBEXPRELL_TCRELL 0xFF
2307 #define FB_SUBEXPRELH_TCRELH 0
2308 #define FM_SUBEXPRELH_TCRELH 0xFF
2312 #define FM_SUBFXCTL_TEEN 0x8
2315 #define FM_SUBFXCTL_TNLFBYP 0x4
2318 #define FM_SUBFXCTL_BEEN 0x2
2320 #define FB_SUBFXCTL_BNLFBYP 0
2321 #define FM_SUBFXCTL_BNLFBYP 0x1