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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_fp0_conv.S14 movi a2, 0
26 assert eqi, a2, 0
31 movi a2, 0
34 movi a2, 0x7c
41 movi a2, 0
55 assert eqi, a2, 0
63 movi a2, (\rm) | 0x7c
69 test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0, \sr
80 test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
81 test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_arria10.h210 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
212 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
214 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
216 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
218 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
220 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
223 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
231 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
245 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dbcm2836.dtsi7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 reg = <0x40000000 0x100>;
29 interrupts = <0>, // PHYS_SECURE_PPI
38 #size-cells = <0>;
41 v7_cpu0: cpu@0 {
44 reg = <0xf00>;
51 reg = <0xf01>;
58 reg = <0xf02>;
[all …]
H A Dbcm2837.dtsi7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 reg = <0x40000000 0x100>;
23 interrupts = <0>, // PHYS_SECURE_PPI
32 #size-cells = <0>;
35 cpu0: cpu@0 {
38 reg = <0>;
40 cpu-release-addr = <0x0 0x000000d8>;
48 cpu-release-addr = <0x0 0x000000e0>;
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
38 bic r0, r0, #0x3f000000 @ bank/f/lock/s
39 bic r0, r0, #0x0000000c @ w-buffer/cache
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mov ip, #0
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
53 bic ip, ip, #0x0000000c @ ............wc..
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
61 mov r0, #0
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi8 ranges = <0x7e000000 0x3f000000 0x1000000>,
9 <0x40000000 0x40000000 0x00001000>;
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 reg = <0x40000000 0x100>;
30 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
39 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
54 cpu-release-addr = <0x0 0x000000d8>;
55 d-cache-size = <0x8000>;
[all …]
H A Dbcm2836.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
51 v7_cpu0: cpu@0 {
54 reg = <0xf00>;
56 d-cache-size = <0x8000>;
59 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dmac.h30 AR_RTSCTSQual##_index : 0))
34 AR_2040_##_index : 0) \
36 AR_GI##_index : 0) \
38 AR_STBC##_index : 0))
71 #define ATH9K_TXERR_XRETRY 0x01
72 #define ATH9K_TXERR_FILT 0x02
73 #define ATH9K_TXERR_FIFO 0x04
74 #define ATH9K_TXERR_XTXOP 0x08
75 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
76 #define ATH9K_TX_ACKED 0x20
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_mips.h5 #define BCMA_MIPS_IPSFLAG 0x0F08
7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000
21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
22 #define BCMA_MIPS_MIPS74K_BIST 0x000C
23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_security_bitdef.h14 #define _SECCAM_ADR_MSK 0x000000FF
15 #define _SECCAM_ADR_SHT 0
20 #define _SEC_CONFIG_MSK 0x3F000000
22 #define _SEC_KEYCONTENT_MSK 0x00FFFFFF
23 #define _SEC_KEYCONTENT_SHT 0
31 #define _TXUSEDK BIT(0)
/openbmc/linux/arch/arm/nwfpe/
H A Dfpopcode.c19 { .high = 0x0000, .low = 0x0000000000000000ULL},/* extended 0.0 */
20 { .high = 0x3fff, .low = 0x8000000000000000ULL},/* extended 1.0 */
21 { .high = 0x4000, .low = 0x8000000000000000ULL},/* extended 2.0 */
22 { .high = 0x4000, .low = 0xc000000000000000ULL},/* extended 3.0 */
23 { .high = 0x4001, .low = 0x8000000000000000ULL},/* extended 4.0 */
24 { .high = 0x4001, .low = 0xa000000000000000ULL},/* extended 5.0 */
25 { .high = 0x3ffe, .low = 0x8000000000000000ULL},/* extended 0.5 */
26 { .high = 0x4002, .low = 0xa000000000000000ULL},/* extended 10.0 */
31 0x0000000000000000ULL, /* double 0.0 */
32 0x3ff0000000000000ULL, /* double 1.0 */
[all …]
/openbmc/qemu/hw/arm/
H A Dbcm2836.c22 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
30 for (n = 0; n < bc->core_count; n++) { in bcm283x_base_init()
80 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 0, bc->peri_base, 1); in bcm283x_common_realize()
95 if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { in bcm2835_realize()
100 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, in bcm2835_realize()
101 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); in bcm2835_realize()
103 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); in bcm2835_realize()
124 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); in bcm2836_realize()
126 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, in bcm2836_realize()
127 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); in bcm2836_realize()
[all …]
/openbmc/linux/arch/mips/math-emu/
H A Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
H A Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
84 flash@0 {
89 reg = <0>; /* Chip select 0 */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_global_conf_masks.h24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
25 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
29 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
33 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
37 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
39 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
41 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
[all …]
/openbmc/u-boot/include/
H A Dmpc106.h14 #define PCIDEVID_MPC106 0x0
19 #define MPC106_REG 0x80000000
22 #define MPC106_REG_ADDR 0x80000cf8
23 #define MPC106_REG_DATA 0x80000cfc
24 #define MPC106_ISA_IO_PHYS 0x80000000
25 #define MPC106_ISA_IO_BUS 0x00000000
26 #define MPC106_ISA_IO_SIZE 0x00800000
27 #define MPC106_PCI_IO_PHYS 0x81000000
28 #define MPC106_PCI_IO_BUS 0x01000000
29 #define MPC106_PCI_IO_SIZE 0x3e800000
[all …]
/openbmc/qemu/linux-user/arm/nwfpe/
H A Dfpopcode.c30 { 0x0000000000000000ULL, 0x0000}, /* extended 0.0 */
31 { 0x8000000000000000ULL, 0x3fff}, /* extended 1.0 */
32 { 0x8000000000000000ULL, 0x4000}, /* extended 2.0 */
33 { 0xc000000000000000ULL, 0x4000}, /* extended 3.0 */
34 { 0x8000000000000000ULL, 0x4001}, /* extended 4.0 */
35 { 0xa000000000000000ULL, 0x4001}, /* extended 5.0 */
36 { 0x8000000000000000ULL, 0x3ffe}, /* extended 0.5 */
37 { 0xa000000000000000ULL, 0x4002} /* extended 10.0 */
41 const_float64(0x0000000000000000ULL), /* double 0.0 */
42 const_float64(0x3ff0000000000000ULL), /* double 1.0 */
[all …]
/openbmc/linux/arch/m68k/fpsp040/
H A Dsatanh.S38 | atan(X) := sgn / (+0).
41 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
71 andil #0x7FFFFFFF,%d0
72 cmpil #0x3FFF8000,%d0
82 fadds #0x3F800000,%fp1 | ...1-Y
85 andil #0x80000000,%d0
86 oril #0x3F000000,%d0 | ...SIGN(X)*HALF
99 fcmps #0x3F800000,%fp0
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]

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