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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dls2080ardb.h19 #define I2C_MUX_CH_VOL_MONITOR 0xa
20 #define I2C_VOL_MONITOR_ADDR 0x38
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1 0x51
48 #define SPD_EEPROM_ADDRESS2 0x52
49 #define SPD_EEPROM_ADDRESS3 0x53
50 #define SPD_EEPROM_ADDRESS4 0x54
51 #define SPD_EEPROM_ADDRESS5 0x55
52 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
54 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
[all …]
H A Dlx2160a_common.h20 #define CONFIG_SYS_FLASH_BASE 0x20000000
29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
33 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS1 0x51
40 #define SPD_EEPROM_ADDRESS2 0x52
41 #define SPD_EEPROM_ADDRESS3 0x53
42 #define SPD_EEPROM_ADDRESS4 0x54
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/openbmc/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]
/openbmc/linux/drivers/staging/media/atomisp/i2c/
H A Dov2722.h38 #define I2C_MSG_LENGTH 0x2
47 * bits 31-16: numerator, bits 15-0: denominator
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
53 * bits 31-16: numerator, bits 15-0: denominator
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
62 * bits 7-0: min f-number denominator
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID 0x2720
66 #define OV2722_ID 0x2722
68 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vpu_init.c14 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
15 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
16 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
28 0x15561500, 0x14561600, 0x13561700, 0x12561800,
29 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
30 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
31 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
32 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
33 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
34 0x05473301, 0x05463401, 0x04453601, 0x04433702,
[all …]
/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/openbmc/qemu/scsi/
H A Dutils.c23 if ((buf[0] >> 5) == 0 && buf[4] == 0) { in scsi_data_cdb_xfer()
32 switch (buf[0] >> 5) { in scsi_cdb_xfer()
33 case 0: in scsi_cdb_xfer()
39 return ldl_be_p(&buf[10]) & 0xffffffffULL; in scsi_cdb_xfer()
41 return ldl_be_p(&buf[6]) & 0xffffffffULL; in scsi_cdb_xfer()
52 switch (buf[0] >> 5) { in scsi_cmd_lba()
53 case 0: in scsi_cmd_lba()
54 lba = ldl_be_p(&buf[0]) & 0x1fffff; in scsi_cmd_lba()
59 lba = ldl_be_p(&buf[2]) & 0xffffffffULL; in scsi_cmd_lba()
75 switch (buf[0] >> 5) { in scsi_cdb_length()
[all …]
/openbmc/linux/include/soc/fsl/qe/
H A Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/openbmc/linux/drivers/scsi/
H A Dg_NCR5380.c69 #define NCR53C400_mem_base 0x3880
70 #define NCR53C400_host_buffer 0x3900
71 #define NCR53C400_region_size 0x3a00
73 #define BOARD_NCR5380 0
92 module_param_hw(ncr_irq, int, irq, 0);
93 module_param_hw(ncr_addr, int, ioport, 0);
94 module_param(ncr_5380, int, 0);
95 module_param(ncr_53c400, int, 0);
96 module_param(ncr_53c400a, int, 0);
97 module_param(dtc_3181e, int, 0);
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
100 reg = <0x1>;
106 reg = <0x2>;
112 reg = <0x3>;
118 reg = <0x100>;
124 reg = <0x101>;
130 reg = <0x102>;
[all …]
/openbmc/u-boot/include/linux/
H A Dimmap_qe.h16 #define QE_MURAM_SIZE 0xc000UL
20 #define QE_MURAM_SIZE 0x4000UL
27 #define QE_MURAM_SIZE 0x6000UL
33 #define QE_IMMR_OFFSET 0x00140000
35 #define QE_IMMR_OFFSET 0x01400000
42 u8 res0[0x4];
44 u8 res1[0x70];
60 u8 res0[0x4];
63 u8 res1[0x4];
65 u8 res2[0x20];
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dimx335.c20 #define IMX335_REG_MODE_SELECT 0x3000
21 #define IMX335_MODE_STANDBY 0x01
22 #define IMX335_MODE_STREAMING 0x00
25 #define IMX335_REG_LPFR 0x3030
28 #define IMX335_REG_ID 0x3912
29 #define IMX335_ID 0x00
32 #define IMX335_REG_SHUTTER 0x3058
36 #define IMX335_EXPOSURE_DEFAULT 0x0648
39 #define IMX335_REG_AGAIN 0x30e8
40 #define IMX335_AGAIN_MIN 0
[all …]
H A Dhi846.c22 #define HI846_REG_FLL 0x0006
23 #define HI846_FLL_MAX 0xffff
26 #define HI846_REG_LLP 0x0008
29 #define HI846_REG_BINNING_MODE 0x000c
31 #define HI846_REG_IMAGE_ORIENTATION 0x000e
33 #define HI846_REG_UNKNOWN_0022 0x0022
35 #define HI846_REG_Y_ADDR_START_VACT_H 0x0026
36 #define HI846_REG_Y_ADDR_START_VACT_L 0x0027
37 #define HI846_REG_UNKNOWN_0028 0x0028
39 #define HI846_REG_Y_ADDR_END_VACT_H 0x002c
[all …]
/openbmc/u-boot/drivers/video/
H A Dformike.c12 #define TAG_READ 0x80
13 #define TAG_WRITE 0x00
15 #define TAG_DATA 0x40
16 #define TAG_COMMAND 0x00
18 #define TAG_ADDR_H 0x20
19 #define TAG_ADDR_L 0x00
28 buf[0] = tag; in spi_write_tag_val()
30 buf[0] = val; in spi_write_tag_val()
52 (addr & 0xff00) >> 8); in spi_write_com()
54 (addr & 0x00ff) >> 0); in spi_write_com()
[all …]
/openbmc/linux/include/linux/qed/
H A Dcommon_hsi.h16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
97 #define FW_ENGINEERING_VERSION 0
158 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
161 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
163 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
[all …]
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz_common.c35 #define MIB_COUNTER_NUM 0x20
114 { 0x00, "rx" },
115 { 0x01, "rx_hi" },
116 { 0x02, "rx_undersize" },
117 { 0x03, "rx_fragments" },
118 { 0x04, "rx_oversize" },
119 { 0x05, "rx_jabbers" },
120 { 0x06, "rx_symbol_err" },
121 { 0x07, "rx_crc_err" },
122 { 0x08, "rx_align_err" },
[all …]

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