Lines Matching +full:0 +full:x3a00
12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
31 #define CONFIG_ENV_SIZE 0x20000
57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
59 #define SPD_EEPROM_ADDRESS 0x51
60 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
80 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
81 FTIM0_NOR_TEADC(0x1) | \
82 FTIM0_NOR_TEAHC(0x1))
83 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
84 FTIM1_NOR_TRAD_NOR(0x1))
85 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
86 FTIM2_NOR_TCH(0x0) | \
87 FTIM2_NOR_TWP(0x1))
88 #define CONFIG_SYS_NOR_FTIM3 0x04000000
89 #define CONFIG_SYS_IFC_CCR 0x01000000
112 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
130 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
131 FTIM0_NAND_TWP(0x18) | \
132 FTIM0_NAND_TWCHT(0x07) | \
133 FTIM0_NAND_TWH(0x0a))
134 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
135 FTIM1_NAND_TWBE(0x39) | \
136 FTIM1_NAND_TRR(0x0e) | \
137 FTIM1_NAND_TRP(0x18))
138 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
139 FTIM2_NAND_TREH(0x0a) | \
140 FTIM2_NAND_TWHRE(0x1e))
141 #define CONFIG_SYS_NAND_FTIM3 0x0
154 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
155 #define QIXIS_BRDCFG4_OFFSET 0x54
157 #define QIXIS_QMAP_MASK 0xe0
159 #define QIXIS_LBMAP_MASK 0x1f
161 #define QIXIS_LBMAP_DFLTBANK 0x00
162 #define QIXIS_LBMAP_ALTBANK 0x20
163 #define QIXIS_LBMAP_SD 0x00
164 #define QIXIS_LBMAP_EMMC 0x00
165 #define QIXIS_LBMAP_SD_QSPI 0x00
166 #define QIXIS_LBMAP_QSPI 0x00
167 #define QIXIS_RCW_SRC_SD 0x40
168 #define QIXIS_RCW_SRC_EMMC 0x41
169 #define QIXIS_RCW_SRC_QSPI 0x62
170 #define QIXIS_RST_CTL_RESET 0x31
171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
174 #define QIXIS_RST_FORCE_MEM 0x01
176 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
187 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
189 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
195 FTIM2_GPCM_TCH(0xf) | \
196 FTIM2_GPCM_TWP(0x3E))
197 #define SYS_FPGA_CS_FTIM3 0x0
232 #define I2C_MUX_CH_VOL_MONITOR 0xA
234 #define I2C_VOL_MONITOR_ADDR 0x63
235 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
236 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
238 #define I2C_SVDD_MONITOR_ADDR 0x4F
251 #define PMBUS_CMD_PAGE 0x0
252 #define PMBUS_CMD_READ_VOUT 0x8B
253 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
254 #define PMBUS_CMD_VOUT_COMMAND 0x21
256 #define PWM_CHANNEL0 0x0
261 #define I2C_MUX_PCA_ADDR_PRI 0x77
262 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
263 #define I2C_RETIMER_ADDR 0x18
264 #define I2C_MUX_CH_DEFAULT 0x8
265 #define I2C_MUX_CH5 0xD
273 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
280 #define CONFIG_SYS_EEPROM_BUS_NUM 0
281 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
296 #define CONFIG_SYS_MEMTEST_START 0x80000000
297 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
311 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
312 "sf read 0x80100000 0xE00000 0x100000;" \
314 "sf read 0x80700000 0x700000 0x40000 && " \
315 "sf read 0x80740000 0x740000 0x40000 && " \
316 "esbc_validate 0x80700000 && " \
317 "esbc_validate 0x80740000 ;" \
318 "fsl_mc start mc 0x80000000 0x80100000\0"
320 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
321 "mmc read 0x80100000 0x7000 0x800;" \
323 "mmc read 0x80700000 0x3800 0x10 && " \
324 "mmc read 0x80740000 0x3A00 0x10 && " \
325 "esbc_validate 0x80700000 && " \
326 "esbc_validate 0x80740000 ;" \
327 "fsl_mc start mc 0x80000000 0x80100000\0"
331 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
332 "sf read 0x80100000 0xE00000 0x100000;" \
334 "sf read 0x80700000 0x700000 0x40000 && " \
335 "sf read 0x80740000 0x740000 0x40000 && " \
336 "esbc_validate 0x80700000 && " \
337 "esbc_validate 0x80740000 ;" \
338 "fsl_mc start mc 0x80000000 0x80100000\0" \
339 "mcmemsize=0x70000000\0"
342 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
343 "mmc read 0x80100000 0x7000 0x800;" \
345 "mmc read 0x80700000 0x3800 0x10 && " \
346 "mmc read 0x80740000 0x3A00 0x10 && " \
347 "esbc_validate 0x80700000 && " \
348 "esbc_validate 0x80740000 ;" \
349 "fsl_mc start mc 0x80000000 0x80100000\0" \
350 "mcmemsize=0x70000000\0"
357 "BOARD=ls1088ardb\0" \
358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
359 "ramdisk_addr=0x800000\0" \
360 "ramdisk_size=0x2000000\0" \
361 "fdt_high=0xa0000000\0" \
362 "initrd_high=0xffffffffffffffff\0" \
363 "fdt_addr=0x64f00000\0" \
364 "kernel_addr=0x1000000\0" \
365 "kernel_addr_sd=0x8000\0" \
366 "kernelhdr_addr_sd=0x4000\0" \
367 "kernel_start=0x580100000\0" \
368 "kernelheader_start=0x580800000\0" \
369 "scriptaddr=0x80000000\0" \
370 "scripthdraddr=0x80080000\0" \
371 "fdtheader_addr_r=0x80100000\0" \
372 "kernelheader_addr=0x800000\0" \
373 "kernelheader_addr_r=0x80200000\0" \
374 "kernel_addr_r=0x81000000\0" \
375 "kernelheader_size=0x40000\0" \
376 "fdt_addr_r=0x90000000\0" \
377 "load_addr=0xa0000000\0" \
378 "kernel_size=0x2800000\0" \
379 "kernel_size_sd=0x14000\0" \
380 "kernelhdr_size_sd=0x10\0" \
382 "mcmemsize=0x70000000\0" \
384 "boot_scripts=ls1088ardb_boot.scr\0" \
385 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
395 "done\0" \
403 "source ${scriptaddr}\0" \
404 "installer=load mmc 0:2 $load_addr " \
407 "mmc read 0x80001000 0x6800 0x800;" \
408 "fsl_mc lazyapply dpl 0x80001000;" \
409 "bootm $load_addr#ls1088ardb\0" \
415 "bootm $load_addr#$BOARD\0" \
422 "bootm $load_addr#$BOARD\0"
425 "BOARD=ls1088ardb\0" \
426 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
427 "ramdisk_addr=0x800000\0" \
428 "ramdisk_size=0x2000000\0" \
429 "fdt_high=0xa0000000\0" \
430 "initrd_high=0xffffffffffffffff\0" \
431 "fdt_addr=0x64f00000\0" \
432 "kernel_addr=0x1000000\0" \
433 "kernel_addr_sd=0x8000\0" \
434 "kernelhdr_addr_sd=0x4000\0" \
435 "kernel_start=0x580100000\0" \
436 "kernelheader_start=0x580800000\0" \
437 "scriptaddr=0x80000000\0" \
438 "scripthdraddr=0x80080000\0" \
439 "fdtheader_addr_r=0x80100000\0" \
440 "kernelheader_addr=0x800000\0" \
441 "kernelheader_addr_r=0x80200000\0" \
442 "kernel_addr_r=0x81000000\0" \
443 "kernelheader_size=0x40000\0" \
444 "fdt_addr_r=0x90000000\0" \
445 "load_addr=0xa0000000\0" \
446 "kernel_size=0x2800000\0" \
447 "kernel_size_sd=0x14000\0" \
448 "kernelhdr_size_sd=0x10\0" \
451 "boot_scripts=ls1088ardb_boot.scr\0" \
452 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
462 "done\0" \
470 "source ${scriptaddr}\0" \
471 "installer=load mmc 0:2 $load_addr " \
474 "mmc read 0x80001000 0x6800 0x800;" \
475 "fsl_mc lazyapply dpl 0x80001000;" \
476 "bootm $load_addr#ls1088ardb\0" \
482 "bootm $load_addr#$BOARD\0" \
489 "bootm $load_addr#$BOARD\0"
495 "sf read 0x80001000 0xd00000 0x100000;" \
497 " && sf read 0x80780000 0x780000 0x100000 " \
498 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
499 "&& fsl_mc lazyapply dpl 0x80001000;" \
504 "mmc read 0x80001000 0x6800 0x800; " \
506 " && mmc read 0x80780000 0x3C00 0x10 " \
507 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
508 "&& fsl_mc lazyapply dpl 0x80001000;" \
515 "sf read 0x80001000 0xd00000 0x100000;" \
517 " && sf read 0x80780000 0x780000 0x100000 " \
518 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
519 "&& fsl_mc lazyapply dpl 0x80001000;" \
527 "mmc read 0x80001000 0x6800 0x800; " \
529 " && mmc read 0x80780000 0x3C00 0x10 " \
530 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
531 "&& fsl_mc lazyapply dpl 0x80001000;" \
542 #define AQ_PHY_ADDR1 0x00
543 #define AQR105_IRQ_MASK 0x00000004
545 #define QSGMII1_PORT1_PHY_ADDR 0x0c
546 #define QSGMII1_PORT2_PHY_ADDR 0x0d
547 #define QSGMII1_PORT3_PHY_ADDR 0x0e
548 #define QSGMII1_PORT4_PHY_ADDR 0x0f
549 #define QSGMII2_PORT1_PHY_ADDR 0x1c
550 #define QSGMII2_PORT2_PHY_ADDR 0x1d
551 #define QSGMII2_PORT3_PHY_ADDR 0x1e
552 #define QSGMII2_PORT4_PHY_ADDR 0x1f
567 func(MMC, mmc, 0) \
568 func(SCSI, scsi, 0) \