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/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]
H A Dibm-power10-dual.dtsi8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
12 cfam@0,0 {
13 reg = <0 0>;
16 chip-id = <0>;
20 reg = <0x1000 0x400>;
25 reg = <0x1800 0x400>;
27 #size-cells = <0>;
29 cfam0_i2c0: i2c-bus@0 {
31 #size-cells = <0>;
[all …]
H A Dibm-power11-quad.dtsi126 #size-cells = <0>;
129 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
131 cfam@0,0 {
132 reg = <0 0>;
135 chip-id = <0>;
139 reg = <0x1000 0x400>;
144 reg = <0x1800 0x400>;
146 #size-cells = <0>;
148 cfam0_i2c0: i2c-bus@0 {
149 reg = <0>; /* OMI01 */
[all …]
H A Daspeed-bmc-opp-palmetto.dts17 reg = <0x40000000 0x20000000>;
27 reg = <0x5f000000 0x01000000>; /* 16M */
31 reg = <0x5ee00000 0x00200000>;
37 reg = <0x5C000000 0x02000000>; /* 32MB */
60 #size-cells = <0>;
69 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
86 flash@0 {
98 pinctrl-0 = <&pinctrl_spi1debug_default>;
100 flash@0 {
110 pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
[all …]
H A Daspeed-bmc-opp-tacoma.dts21 reg = <0x80000000 0x40000000>;
31 reg = <0xb8000000 0x4000000>; /* 64M */
36 reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
37 record-size = <0x8000>;
38 console-size = <0x8000>;
39 pmsg-size = <0x8000>;
46 reg = <0xbf000000 0x01000000>; /* 16M */
97 io-channels = <&dps 0>;
142 flash@0 {
161 pinctrl-0 = <&pinctrl_spi1_default>;
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Drcb.h9 #define ACPIIRQEN 0x31e0 /* 32bit */
11 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
12 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
14 #define DEEP_S3_POL 0x3328 /* 32bit */
15 #define DEEP_S3_EN_AC (1 << 0)
17 #define DEEP_S5_POL 0x3330 /* 32bit */
20 #define DEEP_SX_CONFIG 0x3334 /* 32bit */
23 #define DEEP_SX_GP27_PIN_EN (1 << 0)
24 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
25 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dlpc_common.h9 #define PCH_RCBA_BASE 0xf0
11 #define RC 0x3400 /* 32bit */
12 #define GCS 0x3410 /* 32bit */
14 #define PMBASE 0x40
15 #define ACPI_CNTL 0x44
17 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
18 #define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
19 #define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
20 #define LPC_EN 0x82 /* LPC IF Enables Register */
21 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dqspi.h14 u16 mr; /* 0x00 Mode */
16 u16 dlyr; /* 0x04 Delay */
18 u16 wr; /* 0x08 Wrap */
20 u16 ir; /* 0x0C Interrupt */
22 u16 ar; /* 0x10 Address */
24 u16 dr; /* 0x14 Data */
29 #define QSPI_QMR_MSTR (0x8000)
30 #define QSPI_QMR_DOHIE (0x4000)
31 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
32 #define QSPI_QMR_BITS_MASK (0xC3FF)
[all …]
/openbmc/linux/include/dt-bindings/pinctrl/
H A Ddra.h13 #define MUX_MODE0 0x0
14 #define MUX_MODE1 0x1
15 #define MUX_MODE2 0x2
16 #define MUX_MODE3 0x3
17 #define MUX_MODE4 0x4
18 #define MUX_MODE5 0x5
19 #define MUX_MODE6 0x6
20 #define MUX_MODE7 0x7
21 #define MUX_MODE8 0x8
22 #define MUX_MODE9 0x9
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Ddra.h16 #define MUX_MODE0 0x0
17 #define MUX_MODE1 0x1
18 #define MUX_MODE2 0x2
19 #define MUX_MODE3 0x3
20 #define MUX_MODE4 0x4
21 #define MUX_MODE5 0x5
22 #define MUX_MODE6 0x6
23 #define MUX_MODE7 0x7
24 #define MUX_MODE8 0x8
25 #define MUX_MODE9 0x9
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
54 reg = <0x3100>;
56 #size-cells = <0>;
57 interrupts = <PMK8350_SID 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dpm8998.dtsi35 pm8998_lsid0: pmic@0 {
37 reg = <0x0 SPMI_USID>;
39 #size-cells = <0>;
44 reg = <0x800>;
45 mode-bootloader = <0x2>;
46 mode-recovery = <0x1>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
67 reg = <0x2400>;
68 interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dsc8280xp-pmics.dtsi14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
40 hysteresis = <0>;
46 hysteresis = <0>;
55 pmk8280: pmic@0 {
57 reg = <0x0 SPMI_USID>;
59 #size-cells = <0>;
63 reg = <0x1300>, <0x800>;
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
[all …]
/openbmc/phosphor-logging/extensions/openpower-pels/registry/
H A Dmessage_registry.json9 "ReasonCode": "0x1001",
31 "ReasonCode": "0x1002",
52 "ReasonCode": "0x1003",
68 "ReasonCode": "0x1004",
85 "ReasonCode": "0x1005",
102 "ReasonCode": "0x1006",
117 "ReasonCode": "0x1007",
146 "ReasonCode": "0x1008",
175 "ReasonCode": "0x1009",
204 "ReasonCode": "0x100A",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-spmi-adc-tm-hc.yaml31 const: 0
55 "^([-a-z0-9]*)@[0-7]$":
63 minimum: 0
76 channel will be calibrated with 0V and 1.25V reference channels,
81 enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000]
119 #size-cells = <0>;
121 reg = <0x3100>;
124 #size-cells = <0>;
135 reg = <0x3400>;
136 interrupts = <0x2 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dqcom-spmi-adc-tm5.yaml34 const: 0
60 "^([-a-z0-9]*)@[0-7]$":
68 minimum: 0
81 channel will be calibrated with 0V and 1.25V reference channels,
140 "^([-a-z0-9]*)@[0-7]$":
172 #size-cells = <0>;
174 reg = <0x3100>;
177 #size-cells = <0>;
191 reg = <0x3500>;
192 interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Domap.h15 #define SMX_APE_BASE 0x68000000
18 #define OMAP34XX_GPMC_BASE 0x6E000000
21 #define OMAP34XX_SMS_BASE 0x6C000000
24 #define OMAP34XX_SDRC_BASE 0x6D000000
29 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
32 #define OMAP34XX_L4_PER 0x49000000
36 #define OMAP34XX_DMA4_BASE 0x48056000
39 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dtegra186_gpio.c66 return 0; in tegra186_gpio_set_out()
82 return 0; in tegra186_gpio_set_val()
95 ret = tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_direction_output()
122 return tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_set_value()
143 gpio = args->args[0]; in tegra186_gpio_xlate()
149 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in tegra186_gpio_xlate()
151 return 0; in tegra186_gpio_xlate()
177 return 0; in tegra186_gpio_bind()
183 for (port = 0; port < ctlr_data->port_count; port++) { in tegra186_gpio_bind()
200 return 0; in tegra186_gpio_bind()
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsys_nautilus.c75 dev->bus->self && dev->bus->self->device == 0x700f) in nautilus_map_irq()
92 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8); in nautilus_kill_arch()
93 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80); in nautilus_kill_arch()
94 outb(1, 0x92); in nautilus_kill_arch()
95 outb(0, 0x92); in nautilus_kill_arch()
102 off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */ in nautilus_kill_arch()
103 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport); in nautilus_kill_arch()
106 off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */ in nautilus_kill_arch()
107 pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport); in nautilus_kill_arch()
109 pmuport &= 0xfffe; in nautilus_kill_arch()
[all …]

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