/openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
H A D | keystone-reset.txt | 32 in format: <0>, <2>; It can be in random order and 33 begins from 0 to 3, as keystone can contain up to 4 SoC 42 reg = <0x02310000 0x200>; 47 reg = <0x02620000 0x1000>; 52 ti,syscon-pll = <&pllctrl 0xe4>; 53 ti,syscon-dev = <&devctrl 0x328>; 54 ti,wdt-list = <0>; 63 ti,syscon-pll = <&pllctrl 0xe4>; 64 ti,syscon-dev = <&devctrl 0x328>; 65 ti,wdt-list = <0>, <2>;
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/openbmc/linux/drivers/memory/tegra/ |
H A D | tegra210-mc.h | 12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310 14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314 15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | renesas,sdhi.yaml | 103 pinctrl-0: 228 reg = <0xee100000 0x328>; 231 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; 240 reg = <0xee120000 0x328>; 243 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; 252 reg = <0xee140000 0x100>; 255 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; 264 reg = <0xee160000 0x100>; 267 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
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/openbmc/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/ |
H A D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) 9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) 10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) 11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) 12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) 13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) 15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) 16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) 17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) 18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | avivod.h | 31 #define D1CRTC_CONTROL 0x6080 32 #define CRTC_EN (1 << 0) 33 #define D1CRTC_STATUS 0x609c 34 #define D1CRTC_UPDATE_LOCK 0x60E8 35 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 36 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 38 #define D2CRTC_CONTROL 0x6880 39 #define D2CRTC_STATUS 0x689c 40 #define D2CRTC_UPDATE_LOCK 0x68E8 41 #define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 [all …]
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/openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
H A D | hardware-k2g.h | 15 #define KS2_LPSC_ALWAYSON 0 57 #define KS2_NETCP_PDMA_CTRL_BASE 0x04010000 58 #define KS2_NETCP_PDMA_TX_BASE 0x04011000 60 #define KS2_NETCP_PDMA_RX_BASE 0x04012000 62 #define KS2_NETCP_PDMA_SCHED_BASE 0x04010100 63 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000 68 #define KS2_NETCP_BASE 0x04000000 70 #define K2G_GPIO0_BASE 0X02603000 71 #define K2G_GPIO1_BASE 0X0260a000 72 #define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
H A D | am35x_def.h | 26 #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ 32 #define CONF2_NO_OVERRIDE (0 << 14) 41 #define CONF2_REFFREQ (0xf << 8) 51 #define AM35X_SCM_GEN_BASE 0x48002270 53 u32 res1[0xC4]; /* 0x000 - 0x30C */ 54 u32 devconf2; /* 0x310 */ 55 u32 devconf3; /* 0x314 */ 56 u32 res2[0x2]; /* 0x318 - 0x31C */ 57 u32 cba_priority; /* 0x320 */ 58 u32 lvl_intr_clr; /* 0x324 */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | vt8500.txt | 19 - #clock-cells : from common clock binding; shall be set to 0. 24 - #clock-cells : from common clock binding; shall be set to 0. 47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f 54 #clock-cells = <0>; 60 #clock-cells = <0>; 63 reg = <0x200>; 67 #clock-cells = <0>; 70 divisor-reg = <0x328>; 71 divisor-mask = <0x3f>; 72 enable-reg = <0x254>;
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/openbmc/linux/include/linux/bcma/ |
H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000 8 #define BCMA_GMAC_CMN_STAG1 0x004 9 #define BCMA_GMAC_CMN_STAG2 0x008 10 #define BCMA_GMAC_CMN_STAG3 0x00C 11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020 12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024 13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100 14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff 15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000 17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000 [all …]
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/openbmc/linux/sound/soc/tegra/ |
H A D | tegra186_asrc.h | 13 #define TEGRA186_ASRC_CFG 0x0 14 #define TEGRA186_ASRC_RATIO_INT_PART 0x4 15 #define TEGRA186_ASRC_RATIO_FRAC_PART 0x8 16 #define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc 17 #define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10 18 #define TEGRA186_ASRC_TX_THRESHOLD 0x14 19 #define TEGRA186_ASRC_RX_THRESHOLD 0x18 20 #define TEGRA186_ASRC_RATIO_COMP 0x1c 21 #define TEGRA186_ASRC_RX_STATUS 0x20 22 #define TEGRA186_ASRC_RX_CIF_CTRL 0x24 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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/openbmc/linux/drivers/scsi/cxlflash/ |
H A D | main.h | 25 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0 26 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 27 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624 29 /* Since there is only one target, make it 0 */ 30 #define CXLFLASH_TARGET 0 40 #define FC_MTIP_CMDCONFIG 0x010 41 #define FC_MTIP_STATUS 0x018 42 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ 43 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ 44 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8365.c | 24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 394 0x0ec, 0, 2, 7), 396 MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1), 397 MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1), 398 MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1), 399 MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1), 400 MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1), 401 MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1), 402 MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1), 405 #define CLK_CFG_UPDATE 0x004 [all …]
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H A D | clk-mt6779.c | 640 0x20, 0x24, 0x28, 0, 2, 7, 641 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1), 645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2), 648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4), 650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5), 652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6), 654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7), 657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8), 659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9), [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | g12a.h | 20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 [all …]
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H A D | meson8b.h | 16 * Register offsets from the HardKernel[0] data sheet are listed in comment 20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ 23 #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ 24 #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ 25 #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */ 26 #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ 27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 29 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/ |
H A D | keystone.dtsi | 27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>; 34 reg = <0x0 0x02561000 0x0 0x1000>, 35 <0x0 0x02562000 0x0 0x2000>, 36 <0x0 0x02564000 0x0 0x2000>, 37 <0x0 0x02566000 0x0 0x2000>; 66 cpu_suspend = <0x84000001>; 67 cpu_off = <0x84000002>; 68 cpu_on = <0x84000003>; 71 soc0: soc@0 { 76 ranges = <0x0 0x0 0x0 0xc0000000>; [all …]
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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100 24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120 26 #define mmPCI_NRTR_DBG_E_ARB 0x300 28 #define mmPCI_NRTR_DBG_W_ARB 0x304 30 #define mmPCI_NRTR_DBG_N_ARB 0x308 32 #define mmPCI_NRTR_DBG_S_ARB 0x30C 34 #define mmPCI_NRTR_DBG_L_ARB 0x310 36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 [all …]
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/openbmc/linux/arch/m68k/ |
H A D | Kconfig.machine | 219 Initialize the LCD controller of the 68x328 processor. 224 default 0 226 Reserve certain memory regions on 68x328 based boards. 374 default "0" 377 0, the base of the address space. And this is the default. Some 382 hex "Size of RAM (in bytes), or 0 for automatic" 383 default "0x400000" 385 Define the size of the system RAM. If you select 0 then the 391 default "0" 400 default "0x10000000" [all …]
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20 12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) [all …]
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