1e401fa25SSergey Matyukevich /* SPDX-License-Identifier: GPL-2.0+ */ 2e401fa25SSergey Matyukevich /* Copyright (c) 2018 Quantenna Communications */ 3e401fa25SSergey Matyukevich 4e401fa25SSergey Matyukevich #ifndef __TOPAZ_PCIE_H 5e401fa25SSergey Matyukevich #define __TOPAZ_PCIE_H 6e401fa25SSergey Matyukevich 7e401fa25SSergey Matyukevich /* Topaz PCIe DMA registers */ 8e401fa25SSergey Matyukevich #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) 9e401fa25SSergey Matyukevich #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) 10e401fa25SSergey Matyukevich #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) 11e401fa25SSergey Matyukevich #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) 12e401fa25SSergey Matyukevich #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) 13e401fa25SSergey Matyukevich #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) 14e401fa25SSergey Matyukevich 15e401fa25SSergey Matyukevich #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) 16e401fa25SSergey Matyukevich #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) 17e401fa25SSergey Matyukevich #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) 18e401fa25SSergey Matyukevich #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) 19e401fa25SSergey Matyukevich #define PCIE_DMA_RD_ERR_STATUS_HIGH(base) ((base) + 0x328) 20e401fa25SSergey Matyukevich #define PCIE_DMA_RD_DONE_IMWR_ADDR_LOW(base) ((base) + 0x33c) 21e401fa25SSergey Matyukevich #define PCIE_DMA_RD_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x340) 22e401fa25SSergey Matyukevich 23e401fa25SSergey Matyukevich /* Topaz LHost IPC4 interrupt */ 24e401fa25SSergey Matyukevich #define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C) 25e401fa25SSergey Matyukevich #define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140) 26e401fa25SSergey Matyukevich 27e401fa25SSergey Matyukevich #define TOPAZ_RC_TX_DONE_IRQ (0) 28e401fa25SSergey Matyukevich #define TOPAZ_RC_RST_EP_IRQ (1) 29e401fa25SSergey Matyukevich #define TOPAZ_RC_TX_STOP_IRQ (2) 30e401fa25SSergey Matyukevich #define TOPAZ_RC_RX_DONE_IRQ (3) 31e401fa25SSergey Matyukevich #define TOPAZ_RC_PM_EP_IRQ (4) 32e401fa25SSergey Matyukevich 33e401fa25SSergey Matyukevich /* Topaz LHost M2L interrupt */ 34e401fa25SSergey Matyukevich #define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C) 35e401fa25SSergey Matyukevich #define TOPAZ_CTL_M2L_INT_MASK(base) ((base) + 0x30) 36e401fa25SSergey Matyukevich 37e401fa25SSergey Matyukevich #define TOPAZ_RC_CTRL_IRQ (6) 38e401fa25SSergey Matyukevich 39e401fa25SSergey Matyukevich #define TOPAZ_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16)) 40e401fa25SSergey Matyukevich 41e401fa25SSergey Matyukevich /* PCIe legacy INTx */ 42e401fa25SSergey Matyukevich #define TOPAZ_PCIE_CFG0_OFFSET (0x6C) 43e401fa25SSergey Matyukevich #define TOPAZ_ASSERT_INTX BIT(9) 44e401fa25SSergey Matyukevich 45e401fa25SSergey Matyukevich #endif /* __TOPAZ_PCIE_H */ 46