Home
last modified time | relevance | path

Searched +full:0 +full:x3000000 (Results 1 – 25 of 120) sorted by relevance

12345

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-mini-nand.dts27 memory@0 {
29 reg = <0x0 0x0 0x40000000>;
47 reg = <0x0 0xff100000 0x1000>;
54 partition@0 { /* for testing purpose */
56 reg = <0x0 0x0 0x400000>;
60 reg = <0x0 0x400000 0x1400000>;
64 reg = <0x0 0x1800000 0x400000>;
68 reg = <0x0 0x1C00000 0x1400000>;
72 reg = <0x0 0x3000000 0x400000>;
76 reg = <0x0 0x3400000 0xFCC00000>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts37 memory@0 {
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
79 phy0: phy@0 { /* VSC8211 */
80 reg = <0>;
95 reg = <0x20>;
103 reg = <0x68>;
119 partition@0 { /* for testing purpose */
121 reg = <0x0 0x0 0x400000>;
125 reg = <0x0 0x400000 0x1400000>;
129 reg = <0x0 0x1800000 0x400000>;
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts38 memory@0 {
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
90 ti,rx-internal-delay = <0x8>;
91 ti,tx-internal-delay = <0xa>;
92 ti,fifo-depth = <0x1>;
106 reg = <0x20>;
114 reg = <0x68>;
123 partition@0 { /* for testing purpose */
125 reg = <0x0 0x0 0x400000>;
129 reg = <0x0 0x400000 0x1400000>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-wb50n.dtsi21 reg = <0x20000000 0x4000000>;
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
53 slot@0 {
54 reg = <0>;
61 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
63 atheros@0 {
66 reg = <0>;
76 dmas = <0>, <0>; /* Do not use DMA for dbgu */
84 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
92 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
[all …]
/openbmc/u-boot/include/configs/
H A Dbitmain_antminer_s9.h9 #define CONFIG_SYS_SDRAM_BASE 0x00000000
10 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
15 "autoload=no\0" \
16 "pxefile_addr_r=0x2000000\0" \
17 "scriptaddr=0x3000000\0" \
18 "kernel_addr_r=0x2000000\0" \
19 "fdt_high=0xefff000\0" \
20 "initrd_high=0xefff000\0" \
21 "devnum=0\0" \
22 "wdstop=mw f8005000 ABC000\0" \
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610m4-colibri.dts22 reg = <0x8c000000 0x3000000>;
48 pinctrl-0 = <&pinctrl_uart2>;
56 VF610_PAD_PTD0__UART2_TX 0x21a2
57 VF610_PAD_PTD1__UART2_RX 0x21a1
58 VF610_PAD_PTD2__UART2_RTS 0x21a2
59 VF610_PAD_PTD3__UART2_CTS 0x21a1
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/juno/
H A D0001-configs-vexpress-modify-to-boot-compressed-initramfs.patch17 #define VEXPRESS_RAMDISK_ADDR 0x8fe00000
20 + "kernel_comp_addr_r=0x90000000\0" \
21 + "kernel_comp_size=0x3000000\0" \
22 "kernel_name=norkern\0" \
23 - "kernel_alt_name=Image\0" \
24 + "kernel_alt_name=Image.gz\0" \
25 "ramdisk_name=ramdisk.img\0" \
26 "fdtfile=board.dtb\0" \
27 "fdt_alt_name=juno\0"
/openbmc/u-boot/configs/
H A Dls1088aqds_defconfig3 CONFIG_SYS_TEXT_BASE=0x30100000
13 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dwarp7_defconfig3 CONFIG_SYS_TEXT_BASE=0x87800000
56 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
57 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
63 CONFIG_OPTEE_LOAD_ADDR=0x84000000
64 CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
65 CONFIG_OPTEE_TZDRAM_BASE=0x9d000000
H A Dls1088aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088aqds_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
16 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088ardb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088aqds_sdcard_ifc_defconfig3 CONFIG_SYS_TEXT_BASE=0x80400000
18 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
22 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
H A Dls1088ardb_tfa_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x82000000
18 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088ardb_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
16 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088ardb_tfa_defconfig3 CONFIG_SYS_TEXT_BASE=0x82000000
17 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
H A Dls1088aqds_sdcard_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x80400000
20 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
25 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
H A Dls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x80400000
20 …"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 defau…
26 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0

12345