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/openbmc/linux/arch/arm/mach-s3c/
H A Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
/openbmc/linux/arch/arm/boot/dts/airoha/
H A Den7523.dtsi20 reg = <0x84000000 0xA00000>;
25 reg = <0x84B00000 0x100000>;
30 reg = <0x85000000 0x1A00000>;
35 reg = <0x86B00000 0x100000>;
40 reg = <0x86D00000 0x100000>;
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x1>;
91 reg = <0x1fa20000 0x400>,
[all …]
/openbmc/u-boot/doc/
H A DREADME.ne200020 #define CONFIG_DRIVER_NE2000_BASE (0x20000000+0x300)
24 #define CONFIG_DRIVER_NE2000_CCR (0x28000000+0x3f8)
30 #define CONFIG_DRIVER_NE2000_VAL (0x20)
/openbmc/linux/arch/sh/boards/mach-rsk/
H A Ddevices-rsk7264.c24 [0] = {
25 .start = 0x28000000,
26 .end = 0x280000ff,
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dtoshiba,visconti-dwmac.yaml64 reg = <0 0x28000000 0 0x10000>;
76 #address-cells = <0x1>;
77 #size-cells = <0x0>;
82 reg = <0x1>;
/openbmc/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,lcc.yaml117 reg = <0x28000000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp()
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
/openbmc/linux/arch/arm/configs/
H A Dlpc18xx_defconfig21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
/openbmc/qemu/linux-user/include/host/aarch64/
H A Dhost-signal.h19 #define ESR_MAGIC 0x45535201
62 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ in host_signal_write()
63 return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; in host_signal_write()
73 return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ in host_signal_write()
74 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ in host_signal_write()
75 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ in host_signal_write()
76 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ in host_signal_write()
77 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ in host_signal_write()
78 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ in host_signal_write()
79 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ in host_signal_write()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
H A Dbrcm,iproc-pcie.yaml117 reg = <0x18012000 0x1000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
133 phys = <&phy 0 5>;
137 brcm,pcie-ob-axi-offset = <0x00000000>;
155 reg = <0x18013000 0x1000>;
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dls1021a.dtsi27 #size-cells = <0>;
32 reg = <0xf00>;
39 reg = <0xf01>;
70 reg = <0x1401000 0x1000>,
71 <0x1402000 0x1000>,
72 <0x1404000 0x2000>,
73 <0x1406000 0x2000>;
80 reg = <0x1530000 0x10000>;
86 reg = <0x1ee0000 0x10000>;
92 reg = <0x1560000 0x10000>;
[all …]
H A Dfsl-imx8dx.dtsi37 reg = <0x00000000 0x80000000 0 0x40000000>;
48 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
52 decoder_boot: decoder_boot@0x84000000 {
54 reg = <0 0x84000000 0 0x2000000>;
56 encoder_boot: encoder_boot@0x86000000 {
58 reg = <0 0x86000000 0 0x2000000>;
60 rpmsg_reserved: rpmsg@0x90000000 {
62 reg = <0 0x90000000 0 0x400000>;
64 decoder_rpc: decoder_rpc@0x90400000 {
66 reg = <0 0x90400000 0 0x1000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4337-ciaa.dts35 reg = <0x28000000 0x0800000>; /* 8 MB */
173 pinctrl-0 = <&i2c0_pins>;
178 reg = <0x50>;
183 reg = <0x51>;
188 reg = <0x54>;
196 pinctrl-0 = <&enet_rmii_pins>;
206 pinctrl-0 = <&ssp_pins>;
214 pinctrl-0 = <&uart2_pins>;
220 pinctrl-0 = <&uart3_pins>;
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/openbmc/u-boot/include/configs/
H A Dnovena.h29 #define CONFIG_SYS_MMC_ENV_DEV 0
52 #define CONFIG_SYS_MEMTEST_START 0x10000000
53 #define CONFIG_SYS_MEMTEST_END 0x20000000
66 #define CONFIG_FEC_MXC_PHYADDR 0x7
78 #define CONFIG_SYS_SPD_BUS_NUM 0
87 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
102 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
107 #define CONFIG_DWC_AHSATA_PORT_ID 0
120 #define CONFIG_MXC_USB_FLAGS 0
140 "fdt_high=0xffffffff\0" \
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-evk.dts20 reg = <0x0 0x80000000 0 0x80000000>;
31 size = <0 0x28000000>;
36 reg = <0 0xa8600000 0 0x1000000>;
41 reg = <0 0x1fff8000 0 0x1000>;
46 reg = <0 0xaff00000 0 0x8000>;
51 reg = <0 0xaff08000 0 0x8000>;
56 reg = <0 0xaff10000 0 0x8000>;
61 reg = <0 0xaff18000 0 0x8000>;
67 reg = <0 0xa8400000 0 0x100000>;
76 #clock-cells = <0>;
[all …]
H A Dimx93.dtsi48 #size-cells = <0>;
55 arm,psci-suspend-param = <0x0010033>;
64 A55_0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x100>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
100 #clock-cells = <0>;
128 reg = <0 0x48000000 0 0x10000>,
129 <0 0x48040000 0 0xc0000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3430-sdp.dts15 reg = <0x80000000 0x10000000>; /* 256 MB */
23 reg = <0x48>;
50 ranges = <0 0 0x10000000 0x08000000>,
51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
52 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
54 nor@0,0 {
59 reg = <0 0 0x08000000>;
63 gpmc,cs-on-ns = <0>;
84 partition@0 {
86 reg = <0 0x40000>;
[all …]

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