arm/dts/fsl-imx8dx.dtsi

37 		reg = <0x00000000 0x80000000 0 0x40000000>;
48 		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
52 		decoder_boot: decoder_boot@0x84000000 {
54 			reg = <0 0x84000000 0 0x2000000>;
56 		encoder_boot: encoder_boot@0x86000000 {
58 			reg = <0 0x86000000 0 0x2000000>;
60 		rpmsg_reserved: rpmsg@0x90000000 {
62 			reg = <0 0x90000000 0 0x400000>;
64 		decoder_rpc: decoder_rpc@0x90400000 {
66 			reg = <0 0x90400000 0 0x1000000>;
68 		encoder_rpc: encoder_rpc@0x91400000 {
70 			reg = <0 0x91400000 0 0x1000000>;
72 		dsp_reserved: dsp@0x92400000 {
74 			reg = <0 0x92400000 0 0x2000000>;
76 		decoder_str: str@0x94400000 {
78 			reg = <0 0x94400000 0 0x1800000>;
84 			size = <0 0x28000000>;
85 			alloc-ranges = <0 0x96000000 0 0x28000000>;
92 		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
93 		      <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
103 		reg = <0x0 0x5d1c0000 0x0 0x10000>;
121 		#size-cells = <0>;
126 			#power-domain-cells = <0>;
128 			#size-cells = <0>;
132 				#power-domain-cells = <0>;
137 				#power-domain-cells = <0>;
142 				#power-domain-cells = <0>;
147 				#power-domain-cells = <0>;
152 				#power-domain-cells = <0>;
157 				#power-domain-cells = <0>;
162 				#power-domain-cells = <0>;
167 				#power-domain-cells = <0>;
175 			#power-domain-cells = <0>;
177 			#size-cells = <0>;
181 				#power-domain-cells = <0>;
186 				#power-domain-cells = <0>;
191 				#power-domain-cells = <0>;
196 				#power-domain-cells = <0>;
201 				#power-domain-cells = <0>;
209 			#power-domain-cells = <0>;
211 			#size-cells = <0>;
215 				#power-domain-cells = <0>;
220 				#power-domain-cells = <0>;
225 				#power-domain-cells = <0>;
230 				#power-domain-cells = <0>;
235 				#power-domain-cells = <0>;
244 		reg = <0x0 0x5a800000 0x0 0x4000>;
253 		#size-cells = <0>;
259 		reg = <0x0 0x5a810000 0x0 0x4000>;
269 		#size-cells = <0>;
275 		reg = <0x0 0x5a820000 0x0 0x4000>;
284 		#size-cells = <0>;
290 		reg = <0x0 0x5a830000 0x0 0x4000>;
300 		#size-cells = <0>;
306 		reg = <0x0 0x5d080000 0x0 0x10000>;
317 		reg = <0x0 0x5d090000 0x0 0x10000>;
328 		reg = <0x0 0x5d0a0000 0x0 0x10000>;
339 		reg = <0x0 0x5d0b0000 0x0 0x10000>;
350 		reg = <0x0 0x5d0c0000 0x0 0x10000>;
361 		reg = <0x0 0x5d0d0000 0x0 0x10000>;
372 		reg = <0x0 0x5d0e0000 0x0 0x10000>;
383 		reg = <0x0 0x5d0f0000 0x0 0x10000>;
394 		reg = <0x0 0x5a060000 0x0 0x1000>;
409 		reg = <0x0 0x5b010000 0x0 0x10000>;
416 		assigned-clock-rates = <0>, <400000000>;
427 		reg = <0x0 0x5b020000 0x0 0x10000>;
434 		assigned-clock-rates = <0>, <200000000>;
445 		reg = <0x0 0x5b030000 0x0 0x10000>;
452 		assigned-clock-rates = <0>, <200000000>;
459 		reg = <0x0 0x5b040000 0x0 0x10000>;
477 		reg = <0x0 0x5b050000 0x0 0x10000>;