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/openbmc/openbmc/poky/meta/recipes-multimedia/gstreamer/
H A Dgstreamer1.0-plugins-ugly_1.24.10.bb1 require gstreamer1.0-plugins-common.inc
2 require gstreamer1.0-plugins-license.inc
22 DEPENDS += "gstreamer1.0-plugins-base"
24 GST_PLUGIN_SET_HAS_EXAMPLES = "0"
34 PACKAGECONFIG[x264] = "-Dx264=enabled,-Dx264=disabled,x264"
36 GSTREAMER_GPL = "${@bb.utils.filter('PACKAGECONFIG', 'a52dec cdio dvdread mpeg2dec x264', d)}"
44 FILES:${PN}-x264 += "${datadir}/gstreamer-1.0/presets/GstX264Enc.prs"
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/vlc/
H A Dvlc_3.0.21.bb57 x264 \
63 PACKAGECONFIG[x264] = "--enable-x264,--disable-x264,x264"
74 … = "--enable-gst-decode,--disable-gst-decode,gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-p…
134 EXCLUDE_FROM_WORLD = "${@bb.utils.contains("LICENSE_FLAGS_ACCEPTED", "commercial", "0", "1", d)}"
/openbmc/openbmc/meta-raspberrypi/dynamic-layers/multimedia-layer/recipes-multimedia/rpidistro-vlc/
H A Drpidistro-vlc_3.0.17.bb72 x264 alsa harfbuzz jack neon fribidi dvbpsi a52 v4l2 \
76 PACKAGECONFIG[x264] = "--enable-x264,--disable-x264,x264"
86 … = "--enable-gst-decode,--disable-gst-decode,gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-p…
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3288.c20 .route_offset = 0x264,
27 .route_offset = 0x264,
32 #define RK3288_PULL_OFFSET 0x140
33 #define RK3288_PULL_PMU_OFFSET 0x64
42 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
54 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
63 #define RK3288_DRV_PMU_OFFSET 0x70
64 #define RK3288_DRV_GRF_OFFSET 0x1c0
73 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
85 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-ufs-v6.h9 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
10 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
11 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
12 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
14 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
15 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
16 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
17 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
18 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
19 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dcoreboot.txt21 0xc0389481 that resides in the topmost 8 bytes of the area.
30 reg = <0xfdfea000 0x264>,
31 <0xfdfea000 0x16000>;
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h18 #define HHI_GP0_PLL_CNTL 0x40
19 #define HHI_GP0_PLL_CNTL2 0x44
20 #define HHI_GP0_PLL_CNTL3 0x48
21 #define HHI_GP0_PLL_CNTL4 0x4c
22 #define HHI_GP0_PLL_CNTL5 0x50
23 #define HHI_GP0_PLL_STS 0x54
24 #define HHI_GP0_PLL_CNTL1 0x58
25 #define HHI_HIFI_PLL_CNTL 0x80
26 #define HHI_HIFI_PLL_CNTL2 0x84
27 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
H A Dclock-gx.h16 #define SCR 0x2C /* 0x0b offset in data sheet */
17 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
19 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
20 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
26 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
27 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/openbmc/linux/drivers/clk/meson/
H A Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/openbmc/linux/arch/arm/include/asm/
H A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
[all …]
/openbmc/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/openbmc/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r1, =0x000C0000
12 str r1, [r0, #0x4B4]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x4AC]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x27C]
17 ldr r1, =0x00000030
18 str r1, [r0, #0x250]
19 str r1, [r0, #0x24C]
20 str r1, [r0, #0x490]
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/openbmc/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6375-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x05e00000 0x1000>;
90 iommus = <&apps_smmu 0x820 0x2>;
97 reg = <0x05e01000 0x8e030>,
98 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
129 port@0 {
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Diomux-mx25.h32 MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
33 MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
35 MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
36 MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
38 MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
39 MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
41 MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
42 MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
44 MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
45 MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h19 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
20 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
21 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
22 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
23 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
24 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
25 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
26 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
27 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
28 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
[all …]
/openbmc/linux/arch/arm/mach-ux500/
H A Dpm.c20 #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
21 #define PRCM_ARM_WFI_STANDBY_WFI0 0x08
22 #define PRCM_ARM_WFI_STANDBY_WFI1 0x10
23 #define PRCM_IOCR (prcmu_base + 0x310)
24 #define PRCM_IOCR_IOFORCE 0x1
27 #define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
28 #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
30 #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
31 #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
32 #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
[all …]

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