1c6ff132dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2c6ff132dSArnd Bergmann /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h 3c6ff132dSArnd Bergmann * 4c6ff132dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 5c6ff132dSArnd Bergmann * Copyright 2008 Simtec Electronics 6c6ff132dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 7c6ff132dSArnd Bergmann * http://armlinux.simtec.co.uk/ 8c6ff132dSArnd Bergmann * 9c6ff132dSArnd Bergmann * S3C64XX - GPIO register definitions 10c6ff132dSArnd Bergmann */ 11c6ff132dSArnd Bergmann 12c6ff132dSArnd Bergmann #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H 13c6ff132dSArnd Bergmann #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ 14c6ff132dSArnd Bergmann 15c6ff132dSArnd Bergmann /* Base addresses for each of the banks */ 16c6ff132dSArnd Bergmann 17c6ff132dSArnd Bergmann #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) 18c6ff132dSArnd Bergmann 19c6ff132dSArnd Bergmann #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) 20c6ff132dSArnd Bergmann #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) 21c6ff132dSArnd Bergmann #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) 22c6ff132dSArnd Bergmann #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) 23c6ff132dSArnd Bergmann #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) 24c6ff132dSArnd Bergmann #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) 25c6ff132dSArnd Bergmann #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) 26c6ff132dSArnd Bergmann #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) 27c6ff132dSArnd Bergmann #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) 28c6ff132dSArnd Bergmann #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) 29c6ff132dSArnd Bergmann #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) 30c6ff132dSArnd Bergmann #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) 31c6ff132dSArnd Bergmann #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) 32c6ff132dSArnd Bergmann #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) 33c6ff132dSArnd Bergmann #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) 34c6ff132dSArnd Bergmann #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) 35c6ff132dSArnd Bergmann #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) 36c6ff132dSArnd Bergmann 37c6ff132dSArnd Bergmann /* SPCON */ 38c6ff132dSArnd Bergmann 39c6ff132dSArnd Bergmann #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) 40c6ff132dSArnd Bergmann 41c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) 42c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) 43c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) 44c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) 45c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) 46c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) 47c6ff132dSArnd Bergmann 48c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) 49c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) 50c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) 51c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) 52c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) 53c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) 54c6ff132dSArnd Bergmann 55c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) 56c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) 57c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) 58c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) 59c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) 60c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) 61c6ff132dSArnd Bergmann 62c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) 63c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) 64c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) 65c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) 66c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) 67c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) 68c6ff132dSArnd Bergmann 69c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) 70c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) 71c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) 72c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) 73c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) 74c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) 75c6ff132dSArnd Bergmann 76c6ff132dSArnd Bergmann #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) 77c6ff132dSArnd Bergmann 78c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) 79c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) 80c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) 81c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) 82c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) 83c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) 84c6ff132dSArnd Bergmann 85c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) 86c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) 87c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) 88c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) 89c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) 90c6ff132dSArnd Bergmann 91c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) 92c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) 93c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) 94c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) 95c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) 96c6ff132dSArnd Bergmann 97c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) 98c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) 99c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) 100c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) 101c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) 102c6ff132dSArnd Bergmann 103c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) 104c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) 105c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) 106c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) 107c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) 108c6ff132dSArnd Bergmann 109c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_DMPD (1 << 7) 110c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_DPPD (1 << 6) 111c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) 112c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) 113c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) 114c6ff132dSArnd Bergmann 115c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) 116c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) 117c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) 118c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) 119c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) 120c6ff132dSArnd Bergmann 121c6ff132dSArnd Bergmann 122c6ff132dSArnd Bergmann /* External interrupt registers */ 123c6ff132dSArnd Bergmann 124c6ff132dSArnd Bergmann #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) 125c6ff132dSArnd Bergmann #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) 126c6ff132dSArnd Bergmann #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) 127c6ff132dSArnd Bergmann #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) 128c6ff132dSArnd Bergmann #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) 129c6ff132dSArnd Bergmann 130c6ff132dSArnd Bergmann #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) 131c6ff132dSArnd Bergmann #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) 132c6ff132dSArnd Bergmann #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) 133c6ff132dSArnd Bergmann #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) 134c6ff132dSArnd Bergmann #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) 135c6ff132dSArnd Bergmann 136c6ff132dSArnd Bergmann #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) 137c6ff132dSArnd Bergmann #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) 138c6ff132dSArnd Bergmann #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) 139c6ff132dSArnd Bergmann #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) 140c6ff132dSArnd Bergmann #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) 141c6ff132dSArnd Bergmann 142c6ff132dSArnd Bergmann #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) 143c6ff132dSArnd Bergmann #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) 144c6ff132dSArnd Bergmann #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) 145c6ff132dSArnd Bergmann #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) 146c6ff132dSArnd Bergmann #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) 147c6ff132dSArnd Bergmann 148c6ff132dSArnd Bergmann #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) 149c6ff132dSArnd Bergmann #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) 150c6ff132dSArnd Bergmann 151c6ff132dSArnd Bergmann #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) 152c6ff132dSArnd Bergmann #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) 153c6ff132dSArnd Bergmann 154c6ff132dSArnd Bergmann #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) 155c6ff132dSArnd Bergmann #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) 156c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) 157c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) 158c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) 159c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) 160c6ff132dSArnd Bergmann 161c6ff132dSArnd Bergmann #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) 162c6ff132dSArnd Bergmann #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) 163c6ff132dSArnd Bergmann 164c6ff132dSArnd Bergmann /* GPIO sleep configuration */ 165c6ff132dSArnd Bergmann 166c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) 167c6ff132dSArnd Bergmann 168c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) 169c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) 170c6ff132dSArnd Bergmann 171c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) 172c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) 173c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) 174c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) 175c6ff132dSArnd Bergmann 176c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) 177c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) 178c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) 179c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) 180c6ff132dSArnd Bergmann 181c6ff132dSArnd Bergmann 182c6ff132dSArnd Bergmann #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) 183c6ff132dSArnd Bergmann 184c6ff132dSArnd Bergmann #define S3C64XX_SLPEN_USE_xSLP (1 << 0) 185c6ff132dSArnd Bergmann #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) 186c6ff132dSArnd Bergmann 187c6ff132dSArnd Bergmann #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ 188c6ff132dSArnd Bergmann 189