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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dhpe,gxp-i2c.yaml48 reg = <0x2500 0x70>;
51 #size-cells = <0>;
57 reg = <0x50>;
/openbmc/u-boot/include/
H A Dcp437.h4 * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff
8 0x00c7, 0x00fc, 0x00e9, 0x00e2, \
9 0x00e4, 0x00e0, 0x00e5, 0x00e7, \
10 0x00ea, 0x00eb, 0x00e8, 0x00ef, \
11 0x00ee, 0x00ec, 0x00c4, 0x00c5, \
12 0x00c9, 0x00e6, 0x00c6, 0x00f4, \
13 0x00f6, 0x00f2, 0x00fb, 0x00f9, \
14 0x00ff, 0x00d6, 0x00dc, 0x00a2, \
15 0x00a3, 0x00a5, 0x20a7, 0x0192, \
16 0x00e1, 0x00ed, 0x00f3, 0x00fa, \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-armada-370-neta.txt41 reg = <0x70000 0x2500>;
48 bm,pool-long = <0>;
/openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/
H A Dcpu_init.c35 out_be32(&xlbarb->adrto, 0x2000); in cpu_init_f()
36 out_be32(&xlbarb->datto, 0x2500); in cpu_init_f()
37 out_be32(&xlbarb->busto, 0x3000); in cpu_init_f()
42 out_be32(&xlbarb->prien, 0xff); in cpu_init_f()
43 out_be32(&xlbarb->pri, 0); in cpu_init_f()
98 return (0); in cpu_init_r()
104 u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); in uart_port_conf()
108 case 0: in uart_port_conf()
122 clrbits_8(pscsicr, 0x07); in uart_port_conf()
133 setbits_be16(&gpio->par_feci2cirq, 0xf000); in fecpin_setclear()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/openbmc/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/openbmc/qemu/scsi/
H A Dutils.c23 if ((buf[0] >> 5) == 0 && buf[4] == 0) { in scsi_data_cdb_xfer()
32 switch (buf[0] >> 5) { in scsi_cdb_xfer()
33 case 0: in scsi_cdb_xfer()
39 return ldl_be_p(&buf[10]) & 0xffffffffULL; in scsi_cdb_xfer()
41 return ldl_be_p(&buf[6]) & 0xffffffffULL; in scsi_cdb_xfer()
52 switch (buf[0] >> 5) { in scsi_cmd_lba()
53 case 0: in scsi_cmd_lba()
54 lba = ldl_be_p(&buf[0]) & 0x1fffff; in scsi_cmd_lba()
59 lba = ldl_be_p(&buf[2]) & 0xffffffffULL; in scsi_cmd_lba()
75 switch (buf[0] >> 5) { in scsi_cdb_length()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-zynqmp-crf.c20 #define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
44 return 0; in ir_enable_prew()
54 return 0; in ir_disable_prew()
64 for (i = 0; i < CRF_MAX_CPU; i++) { in rst_fpd_apu_prew()
81 .w1c = 0x1,
84 .reset = 0x1,
85 .ro = 0x1,
92 .reset = 0x12c09,
93 .rsvd = 0xf88c80f6,
95 .rsvd = 0x1801210,
[all …]
/openbmc/linux/drivers/media/usb/hdpvr/
H A Dhdpvr.h22 #define HD_PVR_VENDOR_ID 0x2040
23 #define HD_PVR_PRODUCT_ID 0x4900
24 #define HD_PVR_PRODUCT_ID1 0x4901
25 #define HD_PVR_PRODUCT_ID2 0x4902
26 #define HD_PVR_PRODUCT_ID4 0x4903
27 #define HD_PVR_PRODUCT_ID3 0x4982
33 #define HDPVR_FIRMWARE_VERSION 0x08
34 #define HDPVR_FIRMWARE_VERSION_AC3 0x0d
35 #define HDPVR_FIRMWARE_VERSION_0X12 0x12
36 #define HDPVR_FIRMWARE_VERSION_0X15 0x15
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_atmio.c87 .isapnp_id = 0x0000, /* XXX unknown */
89 .ai_maxdata = 0x0fff,
94 .ao_maxdata = 0x0fff,
102 .isapnp_id = 0x1900,
104 .ai_maxdata = 0x0fff,
109 .ao_maxdata = 0x0fff,
117 .isapnp_id = 0x2400,
119 .ai_maxdata = 0x0fff,
124 .ao_maxdata = 0x0fff,
131 .isapnp_id = 0x2500,
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmt6358.c74 CH_L = 0,
108 return 0; in mt6358_set_mtkaif_protocol()
116 0x01f8, 0x01f8); in playback_gpio_set()
118 0xffff, 0x0249); in playback_gpio_set()
120 0xffff, 0x0249); in playback_gpio_set()
131 0x01f8, 0x01f8); in playback_gpio_reset()
133 0x01f8, 0x0000); in playback_gpio_reset()
135 0xf << 8, 0x0); in playback_gpio_reset()
142 0xffff, 0xffff); in capture_gpio_set()
144 0xffff, 0x0249); in capture_gpio_set()
[all …]
/openbmc/qemu/tests/qtest/
H A Dam53c974-test.c21 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow_ok()
22 qtest_outw(s, 0xcfc, 0x01); in test_cmdfifo_underflow_ok()
23 qtest_outl(s, 0xcf8, 0x8000100e); in test_cmdfifo_underflow_ok()
24 qtest_outl(s, 0xcfc, 0x8a000000); in test_cmdfifo_underflow_ok()
25 qtest_outl(s, 0x8a09, 0x42000000); in test_cmdfifo_underflow_ok()
26 qtest_outl(s, 0x8a0d, 0x00); in test_cmdfifo_underflow_ok()
27 qtest_outl(s, 0x8a0b, 0x1000); in test_cmdfifo_underflow_ok()
37 qtest_outl(s, 0xcf8, 0x80001010); in test_cmdfifo_underflow2_ok()
38 qtest_outl(s, 0xcfc, 0xc000); in test_cmdfifo_underflow2_ok()
39 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow2_ok()
[all …]
/openbmc/linux/drivers/leds/
H A Dleds-mlxcpld.c47 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 /* LPC bus access */
50 #define MLXCPLD_LED_OFFSET_HALF 0x01 /* Offset from solid: 3Hz blink */
51 #define MLXCPLD_LED_OFFSET_FULL 0x02 /* Offset from solid: 6Hz blink */
52 #define MLXCPLD_LED_IS_OFF 0x00 /* Off */
53 #define MLXCPLD_LED_RED_STATIC_ON 0x05 /* Solid red */
58 #define MLXCPLD_LED_GREEN_STATIC_ON 0x0D /* Solid green */
130 0x21, 0xf0, MLXCPLD_LED_GREEN_STATIC_ON, 1,
134 0x21, 0xf0, MLXCPLD_LED_RED_STATIC_ON, LED_OFF,
138 0x21, 0x0f, MLXCPLD_LED_GREEN_STATIC_ON, 1,
142 0x21, 0x0f, MLXCPLD_LED_RED_STATIC_ON, LED_OFF,
[all …]
/openbmc/linux/drivers/media/usb/pwc/
H A Dpwc.h46 #define PWC_DEBUG_LEVEL_MODULE BIT(0)
74 } while (0)
86 #define PWC_TRACE(fmt, args...) do { } while(0)
87 #define PWC_DEBUG(level, fmt, args...) do { } while(0)
89 #define pwc_trace 0
97 #define FEATURE_MOTOR_PANTILT 0x0001
98 #define FEATURE_CODEC1 0x0002
99 #define FEATURE_CODEC2 0x0004
127 #define SET_LUM_CTL 0x01
128 #define GET_LUM_CTL 0x02
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/openbmc/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx93.c58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
[all …]
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c18 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
22 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
26 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
30 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
34 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
35 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
36 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
37 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
38 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
39 PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
[all …]
/openbmc/linux/drivers/tty/vt/
H A Dconsolemap.c44 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
45 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
46 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
47 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
48 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
49 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
50 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
51 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
52 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
53 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
[all …]
/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]

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