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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc-common.yaml39 insert event. The default value is 0.
41 default: 0
46 offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A)
/openbmc/linux/include/linux/
H A DmISDNif.h43 * <16 bit 0 >
58 #define MISDN_CMDMASK 0xff00
59 #define MISDN_LAYERMASK 0x00ff
62 #define OPEN_CHANNEL 0x0100
63 #define CLOSE_CHANNEL 0x0200
64 #define CONTROL_CHANNEL 0x0300
65 #define CHECK_DATA 0x0400
68 #define PH_ACTIVATE_REQ 0x0101
69 #define PH_DEACTIVATE_REQ 0x0201
70 #define PH_DATA_REQ 0x2001
[all …]
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc.h22 STATE_IDLE = 0,
33 EVENT_CMD_COMPLETE = 0,
48 TRANS_MODE_PIO = 0,
127 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
267 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
282 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
284 #define DW_MMC_240A 0x240a
285 #define DW_MMC_280A 0x280a
287 #define SDMMC_CTRL 0x000
288 #define SDMMC_PWREN 0x004
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]
/openbmc/linux/drivers/tty/vt/
H A Dconsolemap.c44 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
45 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
46 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
47 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
48 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
49 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
50 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
51 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
52 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
53 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
/openbmc/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
29 …SQ_DEBUG 0x10B1
30 …ne mmSQ_DEBUG_BASE_IDX 0
33 // base address: 0x4980
34 …SDMA0_DEC_START 0x0000
35 …ne mmSDMA0_DEC_START_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
[all …]
/openbmc/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/openbmc/linux/include/linux/mfd/wm8994/
H A Dregisters.h16 #define WM8994_SOFTWARE_RESET 0x00
17 #define WM8994_POWER_MANAGEMENT_1 0x01
18 #define WM8994_POWER_MANAGEMENT_2 0x02
19 #define WM8994_POWER_MANAGEMENT_3 0x03
20 #define WM8994_POWER_MANAGEMENT_4 0x04
21 #define WM8994_POWER_MANAGEMENT_5 0x05
22 #define WM8994_POWER_MANAGEMENT_6 0x06
23 #define WM8994_INPUT_MIXER_1 0x15
24 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
25 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_2_0_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]

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