Lines Matching +full:0 +full:x240a
22 STATE_IDLE = 0,
33 EVENT_CMD_COMPLETE = 0,
48 TRANS_MODE_PIO = 0,
127 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
267 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
282 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
284 #define DW_MMC_240A 0x240a
285 #define DW_MMC_280A 0x280a
287 #define SDMMC_CTRL 0x000
288 #define SDMMC_PWREN 0x004
289 #define SDMMC_CLKDIV 0x008
290 #define SDMMC_CLKSRC 0x00c
291 #define SDMMC_CLKENA 0x010
292 #define SDMMC_TMOUT 0x014
293 #define SDMMC_CTYPE 0x018
294 #define SDMMC_BLKSIZ 0x01c
295 #define SDMMC_BYTCNT 0x020
296 #define SDMMC_INTMASK 0x024
297 #define SDMMC_CMDARG 0x028
298 #define SDMMC_CMD 0x02c
299 #define SDMMC_RESP0 0x030
300 #define SDMMC_RESP1 0x034
301 #define SDMMC_RESP2 0x038
302 #define SDMMC_RESP3 0x03c
303 #define SDMMC_MINTSTS 0x040
304 #define SDMMC_RINTSTS 0x044
305 #define SDMMC_STATUS 0x048
306 #define SDMMC_FIFOTH 0x04c
307 #define SDMMC_CDETECT 0x050
308 #define SDMMC_WRTPRT 0x054
309 #define SDMMC_GPIO 0x058
310 #define SDMMC_TCBCNT 0x05c
311 #define SDMMC_TBBCNT 0x060
312 #define SDMMC_DEBNCE 0x064
313 #define SDMMC_USRID 0x068
314 #define SDMMC_VERID 0x06c
315 #define SDMMC_HCON 0x070
316 #define SDMMC_UHS_REG 0x074
317 #define SDMMC_RST_N 0x078
318 #define SDMMC_BMOD 0x080
319 #define SDMMC_PLDMND 0x084
320 #define SDMMC_DBADDR 0x088
321 #define SDMMC_IDSTS 0x08c
322 #define SDMMC_IDINTEN 0x090
323 #define SDMMC_DSCADDR 0x094
324 #define SDMMC_BUFADDR 0x098
325 #define SDMMC_CDTHRCTL 0x100
326 #define SDMMC_UHS_REG_EXT 0x108
327 #define SDMMC_DDR_REG 0x10c
328 #define SDMMC_ENABLE_SHIFT 0x110
333 #define SDMMC_DBADDRL 0x088
334 #define SDMMC_DBADDRU 0x08c
335 #define SDMMC_IDSTS64 0x090
336 #define SDMMC_IDINTEN64 0x094
337 #define SDMMC_DSCADDRL 0x098
338 #define SDMMC_DSCADDRU 0x09c
339 #define SDMMC_BUFADDRL 0x0A0
340 #define SDMMC_BUFADDRU 0x0A4
344 * Lower than 2.40a : data register offest is 0x100
346 #define DATA_OFFSET 0x100
347 #define DATA_240A_OFFSET 0x200
364 #define SDMMC_CTRL_RESET BIT(0)
367 #define SDMMC_CLKEN_ENABLE BIT(0)
370 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
371 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
372 #define SDMMC_TMOUT_RESP_MSK 0xFF
375 #define SDMMC_CTYPE_4BIT BIT(0)
376 #define SDMMC_CTYPE_1BIT 0
395 #define SDMMC_INT_CD BIT(0)
396 #define SDMMC_INT_ERROR 0xbfc2
414 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
416 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
420 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
421 ((r) & 0xFFF) << 16 | \
422 ((t) & 0xFFF))
424 #define DMA_INTERFACE_IDMA (0x0)
425 #define DMA_INTERFACE_DWDMA (0x1)
426 #define DMA_INTERFACE_GDMA (0x2)
427 #define DMA_INTERFACE_NODMA (0x3)
428 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
429 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
430 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
431 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
439 #define SDMMC_IDMAC_INT_TI BIT(0)
443 #define SDMMC_IDMAC_SWRESET BIT(0)
445 #define SDMMC_RST_HWACTIVE 0x1
447 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
449 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
451 #define SDMMC_CARD_RD_THR_EN BIT(0)
454 #define SDMMC_UHS_18V BIT(0)
458 #define SDMMC_ENABLE_PHASE BIT(0)
547 #define DW_MMC_CARD_PRESENT 0