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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sata2-0.dtsi2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
37 reg = <0x220000 0x1000>;
38 interrupts = <68 0x2 0 0>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Ddavinci_emac.txt32 reg = <0x220000 0x4000>;
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
H A Dmarvell,pp2.yaml32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/
H A Dcbus.h22 #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
23 #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
24 #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
25 #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
26 #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
27 #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
28 #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
29 #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
30 #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
31 #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x4100000 0x800>,
28 <0x4040000 0x100>,
29 <0x4080000 0x800>,
30 <0x40c0000 0x800>;
38 qpend-0 {
[all …]
H A Dkeystone-k2e-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2l-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2g-netcp.dtsi20 queue-range = <0 0x80>;
21 linkram0 = <0x4020000 0x7ff>;
28 managed-queues = <0 0x80>;
29 reg = <0x4100000 0x800>,
30 <0x4040000 0x100>,
31 <0x4080000 0x800>,
32 <0x40c0000 0x800>;
40 qpend-0 {
42 interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
43 0 311 0xf04 0 312 0xf04 0 313 0xf04
[all …]
H A Dkeystone-k2l-netcp.dtsi18 queue-range = <0 0x2000>;
19 linkram0 = <0x100000 0x4000>;
20 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
27 managed-queues = <0 0x2000>;
28 reg = <0x2a40000 0x20000>,
29 <0x2a06000 0x400>,
30 <0x2a02000 0x1000>,
31 <0x2a03000 0x1000>,
32 <0x23a80000 0x20000>,
33 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2e-netcp.dtsi18 queue-range = <0 0x2000>;
19 linkram0 = <0x100000 0x4000>;
20 linkram1 = <0 0x10000>;
27 managed-queues = <0 0x2000>;
28 reg = <0x2a40000 0x20000>,
29 <0x2a06000 0x400>,
30 <0x2a02000 0x1000>,
31 <0x2a03000 0x1000>,
32 <0x23a80000 0x20000>,
33 <0x2a80000 0x20000>;
[all …]
H A Darmada-ap806.dtsi73 reg = <0x0 0x4000000 0x0 0x200000>;
89 ranges = <0x0 0x0 0xf0000000 0x1000000>;
99 reg = <0x210000 0x10000>,
100 <0x220000 0x20000>,
101 <0x240000 0x20000>,
102 <0x260000 0x20000>;
107 reg = <0x280000 0x1000>;
114 reg = <0x290000 0x1000>;
121 reg = <0x2a0000 0x1000>;
128 reg = <0x2b0000 0x1000>;
[all …]
H A Dda850.dtsi20 reg = <0xc0000000 0x0>;
32 reg = <0xfffee000 0x2000>;
38 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
56 reg = <0x11800000 0x40000>,
57 <0x11e00000 0x8000>,
58 <0x11f00000 0x8000>,
59 <0x01c14044 0x4>,
60 <0x01c14174 0x8>;
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,luton.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
43 ranges = <0 0x60000000 0x10200000>;
46 pinctrl-0 = <&uart_pins>;
50 reg = <0x10100000 0x20>;
60 reg = <0x70068 0x68>;
63 gpio-ranges = <&gpio 0 0 32>;
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dhubmd.h29 #define MD_BASE 0x200000
30 #define MD_BASE_PERF 0x210000
31 #define MD_BASE_JUNK 0x220000
33 #define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34 #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35 #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36 #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37 #define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39 #define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi41 reg = <0x0 0x4000000 0x0 0x200000>;
46 reg = <0 0x4400000 0 0x1000000>;
62 ranges = <0x0 0x0 0xf0000000 0x1000000>;
66 reg = <0x100000 0x100000>;
90 reg = <0x210000 0x10000>,
91 <0x220000 0x20000>,
92 <0x240000 0x20000>,
93 <0x260000 0x20000>;
98 reg = <0x280000 0x1000>;
105 reg = <0x290000 0x1000>;
[all …]
H A Darmada-cp11x.dtsi29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 #size-cells = <0>;
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
74 CP11X_LABEL(eth0): ethernet-port@0 {
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
[all …]
/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/openbmc/linux/drivers/net/wireless/intel/ipw2x00/
H A Dipw2100.h41 #define IPW_DL_UNINIT 0x80000000
42 #define IPW_DL_NONE 0x00000000
43 #define IPW_DL_ALL 0x7FFFFFFF
71 #define IPW_DL_ERROR (1<<0)
121 IPW_HW_STATE_ENABLED = 0
159 #define IPW_BD_STATUS_TX_FRAME_802_3 0x00
160 #define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
161 #define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
162 #define IPW_BD_STATUS_TX_FRAME_802_11 0x04
163 #define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs47l85.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
H A Dcs47l90.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]

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