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/openbmc/linux/include/linux/ssb/
H A Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]
/openbmc/u-boot/include/
H A Dfsl_lpuart.h63 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000)
64 #define LPUART_BAUD_OSR_MASK (0x1F000000)
66 #define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000)
67 #define LPUART_BAUD_SBR_MASK (0x1FFF)
68 #define LPUART_BAUD_SBR_SHIFT (0U)
69 #define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF)
70 #define LPUART_BAUD_M10_MASK (0x20000000U)
71 #define LPUART_BAUD_SBNS_MASK (0x2000U)
/openbmc/linux/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
44 reg = <0x101000 0x1000>;
49 reg = <0x102000 0x1000>;
54 reg = <0x103000 0x1000>;
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dgio.h23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
42 * bits 0:6 the product ID; ranges from 0x00 to 0x7F.
43 * bit 7 0=GIO Product ID is 8 bits wide
46 * bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
47 * bit 17 0=no ROM present
52 * IDs above 0x50/0xd0 are of 3rd party boards.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dgoogle,goldfish-pic.txt15 #interrupt-cells = <0x1>;
16 #address-cells = <0>;
23 reg = <0x1f000000 0x1000>;
26 #interrupt-cells = <0x1>;
29 interrupts = <0x2>;
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-ath79.txt7 - #size-cells: <0>, also as required by generic SPI binding.
15 reg = <0x1f000000 0x10>;
18 #size-cells = <0>;
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-ath79.txt9 - #size-cells: <0>, also as required by generic SPI binding.
17 reg = <0x1f000000 0x10>;
23 #size-cells = <0>;
H A Dmikrotik,rb4xx-spi.yaml33 #size-cells = <0>;
35 reg = <0x1f000000 0x10>;
H A Dqca,ar934x-spi.yaml39 reg = <0x1f000000 0x1c>;
42 #size-cells = <0>;
/openbmc/linux/arch/mips/cobalt/
H A Dlcd.c13 .start = 0x1f000000,
14 .end = 0x1f00001f,
35 return 0; in cobalt_lcd_add()
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
H A Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
/openbmc/u-boot/arch/mips/dts/
H A Dqca953x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
43 reg = <0x18040000 0x100>;
62 reg = <0x18020000 0x20>;
72 reg = <0x1f000000 0x10>;
77 #size-cells = <0>;
H A Dar934x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
53 reg = <0x1b000100 0x100>;
60 reg = <0x18020000 0x20>;
66 gmac0: eth@0x19000000 {
68 reg = <0x19000000 0x200>;
76 #size-cells = <0>;
77 phy0: ethernet-phy@0 {
[all …]
H A Dar933x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
43 reg = <0x18040000 0x100>;
62 reg = <0x1b000100 0x100>;
69 reg = <0x18020000 0x20>;
74 gmac0: eth@0x19000000 {
76 reg = <0x19000000 0x200>;
84 #size-cells = <0>;
[all …]
/openbmc/u-boot/include/configs/
H A Dsh7757lcr.h18 #define SH7757LCR_SDRAM_BASE (0x80000000)
20 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
40 #define CONFIG_SYS_MONITOR_BASE 0x00000000
46 #define CONFIG_SH_ETHER_USE_PORT 0
53 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
63 #define CONFIG_SH_SPI_BASE 0xfe002000
66 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
70 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
71 #define SH7757LCR_GRA_OFFSET 0x1f000000
72 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/
H A Dgoya_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_MSG_PROT = 0x7,
23 PACKET_FENCE = 0x8,
24 PACKET_LIN_DMA = 0x9,
25 PACKET_NOP = 0xA,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fault/
H A Dgv100.c34 struct nvkm_fault_buffer *buffer = fault->buffer[0]; in gv100_fault_buffer_process()
45 const u32 instlo = nvkm_ro32(mem, base + 0x00); in gv100_fault_buffer_process()
46 const u32 insthi = nvkm_ro32(mem, base + 0x04); in gv100_fault_buffer_process()
47 const u32 addrlo = nvkm_ro32(mem, base + 0x08); in gv100_fault_buffer_process()
48 const u32 addrhi = nvkm_ro32(mem, base + 0x0c); in gv100_fault_buffer_process()
49 const u32 timelo = nvkm_ro32(mem, base + 0x10); in gv100_fault_buffer_process()
50 const u32 timehi = nvkm_ro32(mem, base + 0x14); in gv100_fault_buffer_process()
51 const u32 info0 = nvkm_ro32(mem, base + 0x18); in gv100_fault_buffer_process()
52 const u32 info1 = nvkm_ro32(mem, base + 0x1c); in gv100_fault_buffer_process()
56 get = 0; in gv100_fault_buffer_process()
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/openbmc/linux/arch/mips/boot/dts/mti/
H A Dmalta.dts7 /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
8 /memreserve/ 0x00001000 0x000ef000; /* YAMON */
9 /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
25 reg = <0x1bdc0000 0x20000>;
56 reg = <0x1e000000 0x400000>;
66 yamon@0 {
68 reg = <0x0 0x100000>;
74 reg = <0x100000 0x2e0000>;
79 reg = <0x3e0000 0x20000>;
87 reg = <0x1f000000 0x1000>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dgf119.c35 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { in gf119_gpio_reset()
37 u8 line = (data & 0x0000003f); in gf119_gpio_reset()
38 u8 defs = !!(data & 0x00000080); in gf119_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in gf119_gpio_reset()
40 u8 unk0 = (data & 0x00ff0000) >> 16; in gf119_gpio_reset()
41 u8 unk1 = (data & 0x1f000000) >> 24; in gf119_gpio_reset()
47 nvkm_gpio_set(gpio, 0, func, line, defs); in gf119_gpio_reset()
49 nvkm_mask(device, 0x00d610 + (line * 4), 0xff, unk0); in gf119_gpio_reset()
51 nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line); in gf119_gpio_reset()
60 nvkm_mask(device, 0x00d610 + (line * 4), 0x00003000, data); in gf119_gpio_drive()
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]

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