1*83d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 26a7b52bcSWills Wang/* 36a7b52bcSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 46a7b52bcSWills Wang */ 56a7b52bcSWills Wang 66a7b52bcSWills Wang#include "skeleton.dtsi" 76a7b52bcSWills Wang 86a7b52bcSWills Wang/ { 96a7b52bcSWills Wang compatible = "qca,ar933x"; 106a7b52bcSWills Wang 116a7b52bcSWills Wang #address-cells = <1>; 126a7b52bcSWills Wang #size-cells = <1>; 136a7b52bcSWills Wang 146a7b52bcSWills Wang cpus { 156a7b52bcSWills Wang #address-cells = <1>; 166a7b52bcSWills Wang #size-cells = <0>; 176a7b52bcSWills Wang 186a7b52bcSWills Wang cpu@0 { 196a7b52bcSWills Wang device_type = "cpu"; 206a7b52bcSWills Wang compatible = "mips,mips24Kc"; 216a7b52bcSWills Wang reg = <0>; 226a7b52bcSWills Wang }; 236a7b52bcSWills Wang }; 246a7b52bcSWills Wang 256a7b52bcSWills Wang clocks { 266a7b52bcSWills Wang #address-cells = <1>; 276a7b52bcSWills Wang #size-cells = <1>; 286a7b52bcSWills Wang ranges; 296a7b52bcSWills Wang 306a7b52bcSWills Wang xtal: xtal { 316a7b52bcSWills Wang #clock-cells = <0>; 326a7b52bcSWills Wang compatible = "fixed-clock"; 336a7b52bcSWills Wang clock-output-names = "xtal"; 346a7b52bcSWills Wang }; 356a7b52bcSWills Wang }; 366a7b52bcSWills Wang 376a7b52bcSWills Wang pinctrl { 386a7b52bcSWills Wang u-boot,dm-pre-reloc; 396a7b52bcSWills Wang compatible = "qca,ar933x-pinctrl"; 406a7b52bcSWills Wang ranges; 416a7b52bcSWills Wang #address-cells = <1>; 426a7b52bcSWills Wang #size-cells = <1>; 436a7b52bcSWills Wang reg = <0x18040000 0x100>; 446a7b52bcSWills Wang }; 456a7b52bcSWills Wang 466a7b52bcSWills Wang ahb { 476a7b52bcSWills Wang compatible = "simple-bus"; 486a7b52bcSWills Wang ranges; 496a7b52bcSWills Wang 506a7b52bcSWills Wang #address-cells = <1>; 516a7b52bcSWills Wang #size-cells = <1>; 526a7b52bcSWills Wang 536a7b52bcSWills Wang apb { 546a7b52bcSWills Wang compatible = "simple-bus"; 556a7b52bcSWills Wang ranges; 566a7b52bcSWills Wang 576a7b52bcSWills Wang #address-cells = <1>; 586a7b52bcSWills Wang #size-cells = <1>; 596a7b52bcSWills Wang 60c3155878SMarek Vasut ehci0: ehci@1b000100 { 61c3155878SMarek Vasut compatible = "generic-ehci"; 62c3155878SMarek Vasut reg = <0x1b000100 0x100>; 63c3155878SMarek Vasut 64c3155878SMarek Vasut status = "disabled"; 65c3155878SMarek Vasut }; 66c3155878SMarek Vasut 676a7b52bcSWills Wang uart0: uart@18020000 { 686a7b52bcSWills Wang compatible = "qca,ar9330-uart"; 696a7b52bcSWills Wang reg = <0x18020000 0x20>; 706a7b52bcSWills Wang 716a7b52bcSWills Wang status = "disabled"; 726a7b52bcSWills Wang }; 732986a9d4SMarek Vasut 742986a9d4SMarek Vasut gmac0: eth@0x19000000 { 7504583c68SWills Wang compatible = "qca,ag933x-mac"; 762986a9d4SMarek Vasut reg = <0x19000000 0x200>; 772986a9d4SMarek Vasut phy = <&phy0>; 782986a9d4SMarek Vasut phy-mode = "rmii"; 792986a9d4SMarek Vasut 802986a9d4SMarek Vasut status = "disabled"; 812986a9d4SMarek Vasut 822986a9d4SMarek Vasut mdio { 832986a9d4SMarek Vasut #address-cells = <1>; 842986a9d4SMarek Vasut #size-cells = <0>; 852986a9d4SMarek Vasut phy0: ethernet-phy@0 { 862986a9d4SMarek Vasut reg = <0>; 872986a9d4SMarek Vasut }; 882986a9d4SMarek Vasut }; 892986a9d4SMarek Vasut }; 902986a9d4SMarek Vasut 912986a9d4SMarek Vasut gmac1: eth@0x1a000000 { 9204583c68SWills Wang compatible = "qca,ag933x-mac"; 932986a9d4SMarek Vasut reg = <0x1a000000 0x200>; 942986a9d4SMarek Vasut phy = <&phy0>; 952986a9d4SMarek Vasut phy-mode = "rgmii"; 962986a9d4SMarek Vasut 972986a9d4SMarek Vasut status = "disabled"; 982986a9d4SMarek Vasut }; 996a7b52bcSWills Wang }; 1006a7b52bcSWills Wang 1016a7b52bcSWills Wang spi0: spi@1f000000 { 1026a7b52bcSWills Wang compatible = "qca,ar7100-spi"; 1036a7b52bcSWills Wang reg = <0x1f000000 0x10>; 1046a7b52bcSWills Wang 1056a7b52bcSWills Wang status = "disabled"; 1066a7b52bcSWills Wang 1076a7b52bcSWills Wang #address-cells = <1>; 1086a7b52bcSWills Wang #size-cells = <0>; 1096a7b52bcSWills Wang }; 1106a7b52bcSWills Wang }; 1116a7b52bcSWills Wang}; 112