1*83d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 2a2277cc3SWills Wang/* 3a2277cc3SWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 4a2277cc3SWills Wang */ 5a2277cc3SWills Wang 6a2277cc3SWills Wang#include "skeleton.dtsi" 7a2277cc3SWills Wang 8a2277cc3SWills Wang/ { 9a2277cc3SWills Wang compatible = "qca,qca953x"; 10a2277cc3SWills Wang 11a2277cc3SWills Wang #address-cells = <1>; 12a2277cc3SWills Wang #size-cells = <1>; 13a2277cc3SWills Wang 14a2277cc3SWills Wang cpus { 15a2277cc3SWills Wang #address-cells = <1>; 16a2277cc3SWills Wang #size-cells = <0>; 17a2277cc3SWills Wang 18a2277cc3SWills Wang cpu@0 { 19a2277cc3SWills Wang device_type = "cpu"; 20a2277cc3SWills Wang compatible = "mips,mips24Kc"; 21a2277cc3SWills Wang reg = <0>; 22a2277cc3SWills Wang }; 23a2277cc3SWills Wang }; 24a2277cc3SWills Wang 25a2277cc3SWills Wang clocks { 26a2277cc3SWills Wang #address-cells = <1>; 27a2277cc3SWills Wang #size-cells = <1>; 28a2277cc3SWills Wang ranges; 29a2277cc3SWills Wang 30a2277cc3SWills Wang xtal: xtal { 31a2277cc3SWills Wang #clock-cells = <0>; 32a2277cc3SWills Wang compatible = "fixed-clock"; 33a2277cc3SWills Wang clock-output-names = "xtal"; 34a2277cc3SWills Wang }; 35a2277cc3SWills Wang }; 36a2277cc3SWills Wang 37a2277cc3SWills Wang pinctrl { 38a2277cc3SWills Wang u-boot,dm-pre-reloc; 39a2277cc3SWills Wang compatible = "qca,qca953x-pinctrl"; 40a2277cc3SWills Wang ranges; 41a2277cc3SWills Wang #address-cells = <1>; 42a2277cc3SWills Wang #size-cells = <1>; 43a2277cc3SWills Wang reg = <0x18040000 0x100>; 44a2277cc3SWills Wang }; 45a2277cc3SWills Wang 46a2277cc3SWills Wang ahb { 47a2277cc3SWills Wang compatible = "simple-bus"; 48a2277cc3SWills Wang ranges; 49a2277cc3SWills Wang 50a2277cc3SWills Wang #address-cells = <1>; 51a2277cc3SWills Wang #size-cells = <1>; 52a2277cc3SWills Wang 53a2277cc3SWills Wang apb { 54a2277cc3SWills Wang compatible = "simple-bus"; 55a2277cc3SWills Wang ranges; 56a2277cc3SWills Wang 57a2277cc3SWills Wang #address-cells = <1>; 58a2277cc3SWills Wang #size-cells = <1>; 59a2277cc3SWills Wang 60a2277cc3SWills Wang uart0: uart@18020000 { 61a2277cc3SWills Wang compatible = "ns16550"; 62a2277cc3SWills Wang reg = <0x18020000 0x20>; 63a2277cc3SWills Wang reg-shift = <2>; 64a2277cc3SWills Wang clock-frequency = <25000000>; 65a2277cc3SWills Wang 66a2277cc3SWills Wang status = "disabled"; 67a2277cc3SWills Wang }; 68a2277cc3SWills Wang }; 69a2277cc3SWills Wang 70a2277cc3SWills Wang spi0: spi@1f000000 { 71a2277cc3SWills Wang compatible = "qca,ar7100-spi"; 72a2277cc3SWills Wang reg = <0x1f000000 0x10>; 73a2277cc3SWills Wang 74a2277cc3SWills Wang status = "disabled"; 75a2277cc3SWills Wang 76a2277cc3SWills Wang #address-cells = <1>; 77a2277cc3SWills Wang #size-cells = <0>; 78a2277cc3SWills Wang }; 79a2277cc3SWills Wang }; 80a2277cc3SWills Wang}; 81