Home
last modified time | relevance | path

Searched +full:0 +full:x1f0000 (Results 1 – 25 of 109) sorted by relevance

12345

/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac-phy.c15 #define EMAC_MDIO_CTRL 0x001414
16 #define EMAC_PHY_STS 0x001418
17 #define EMAC_MDIO_EX_CTRL 0x001440
24 #define MDIO_CLK_SEL_BMSK 0x7000000
29 #define MDIO_REG_ADDR_BMSK 0x1f0000
31 #define MDIO_DATA_BMSK 0xffff
32 #define MDIO_DATA_SHFT 0
35 #define PHY_ADDR_BMSK 0x1f0000
38 #define MDIO_CLK_25_4 0
88 return 0; in emac_mdio_write()
[all …]
/openbmc/linux/drivers/media/rc/
H A Dir-sony-decoder.c44 return 0; in ir_sony_decode()
62 data->count = 0; in ir_sony_decode()
64 return 0; in ir_sony_decode()
74 return 0; in ir_sony_decode()
88 return 0; in ir_sony_decode()
101 return 0; in ir_sony_decode()
119 device = bitrev8((data->bits << 3) & 0xF8); in ir_sony_decode()
120 subdevice = 0; in ir_sony_decode()
121 function = bitrev8((data->bits >> 4) & 0xFE); in ir_sony_decode()
128 device = bitrev8((data->bits >> 0) & 0xFF); in ir_sony_decode()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-sm8150.yaml48 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm6125.yaml47 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sm6115.yaml47 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-qcm2290.yaml47 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sdx55.yaml48 reg = <0x00100000 0x1f0000>;
H A Dqcom,sm6375-gcc.yaml42 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sm6350.yaml49 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc8180x.yaml49 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm8250.yaml50 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc7180.yaml56 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc7280.yaml27 - description: PCIE-0 pipe clock source
29 - description: USF phy rx symbol 0 clock source
31 - description: USF phy tx symbol 0 clock source
67 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sdm845.yaml71 - description: PCIE 0 Pipe clock source
89 reg = <0x100000 0x1f0000>;
H A Dqcom,gcc-sm8350.yaml26 - description: PCIE 0 Pipe clock source (Optional clock)
28 - description: UFS card Rx symbol 0 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
33 - description: UFS phy Tx symbol 0 clock source (Optional clock)
69 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc8280xp.yaml81 reg = <0x00100000 0x1f0000>;
/openbmc/qemu/include/hw/ssi/
H A Dbcm2835_spi.h41 #define RO_MASK 0x1f0000
43 #define BCM2835_SPI_CS 0x00
44 #define BCM2835_SPI_FIFO 0x04
45 #define BCM2835_SPI_CLK 0x08
46 #define BCM2835_SPI_DLEN 0x0c
47 #define BCM2835_SPI_LTOH 0x10
48 #define BCM2835_SPI_DC 0x14
/openbmc/linux/Documentation/i2c/
H A Di2c-stub.rst26 explicitly by setting the respective bits (0x03000000) in the functionality
52 value 0x1f0000 would only enable the quick, byte and byte data
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/lirc/lirc/
H A Dlircd.conf21 pre_data 0x54
25 MUTE 0x70
26 EXIT 0xA8
27 POWER 0xF0
28 CHANNEL_UP 0x50
29 CHANNEL_DOWN 0xD0
30 VOLUME_UP 0x30
31 VOLUME_DOWN 0xB0
32 OK 0x98
33 FAVORITES 0x04
[all …]
/openbmc/linux/drivers/net/mdio/
H A Dmdio-moxart.c16 #define REG_PHY_CTRL 0
22 #define REGAD_MASK 0x3e00000
23 #define PHYAD_MASK 0x1f0000
24 #define MIIRDATA_MASK 0xffff
27 #define MIIWDATA_MASK 0xffff
36 u32 ctrl = 0; in moxart_mdio_read()
54 } while (count > 0); in moxart_mdio_read()
65 u32 ctrl = 0; in moxart_mdio_write()
82 return 0; in moxart_mdio_write()
86 } while (count > 0); in moxart_mdio_write()
[all …]
/openbmc/linux/drivers/devfreq/event/
H A Drockchip-dfi.c26 #define DDRMON_CTRL 0x04
27 #define CLR_DDRMON_CTRL (0x1f0000 << 0)
28 #define LPDDR4_EN (0x10001 << 4)
29 #define HARDWARE_EN (0x10001 << 3)
30 #define LPDDR3_EN (0x10001 << 2)
31 #define SOFTWARE_EN (0x10001 << 1)
32 #define SOFTWARE_DIS (0x10000 << 1)
33 #define TIME_CNT_EN (0x10001 << 0)
35 #define DDRMON_CH0_COUNT_NUM 0x28
36 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]

12345