| /openbmc/linux/drivers/media/platform/chips-media/ |
| H A D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun50i-a100-r.c | 23 { .index = 3, .shift = 0, .width = 5 },
38 .reg = 0x000,
43 0),
47 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
50 .div = _SUNXI_CCU_DIV(0, 2),
53 .reg = 0x00c,
57 0),
73 .reg = 0x010,
78 0),
91 0x11c, BIT(0), 0);
[all …]
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| H A D | ccu-sun50i-h6-r.c | 29 { .index = 3, .shift = 0, .width = 5 },
44 .reg = 0x000,
49 0),
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
69 .reg = 0x010,
74 0),
86 0x11c, BIT(0), 0);
88 0x12c, BIT(0), 0);
90 0x13c, BIT(0), 0);
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | fuse.h | 12 u32 reserved0[64]; /* 0x00 - 0xFC: */
13 u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
14 u32 reserved1[3]; /* 0x104 - 0x10c: */
15 u32 sku_info; /* 0x110 */
16 u32 reserved2[13]; /* 0x114 - 0x144: */
17 u32 fa; /* 0x148: FUSE_FA */
18 u32 reserved3[21]; /* 0x14C - 0x19C: */
19 u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | vf610-pinfunc.h | 18 #define ALT0 0x0
19 #define ALT1 0x1
20 #define ALT2 0x2
21 #define ALT3 0x3
22 #define ALT4 0x4
23 #define ALT5 0x5
24 #define ALT6 0x6
25 #define ALT7 0x7
28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
| H A D | vf610-pinfunc.h | 14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5_matrix.h | 13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
16 u32 res1[20]; /* 0x100 ~ 0x14c */
17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
20 u32 mesr; /* 0x15c: Master Error Status Register */
21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
22 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
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| /openbmc/u-boot/include/dt-bindings/pinctrl/ |
| H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,edp-phy.yaml | 44 const: 0
66 reg = <0x0aec2a00 0x1c0>,
67 <0x0aec2200 0xa0>,
68 <0x0aec2600 0xa0>,
69 <0x0aec2000 0x19c>;
71 clocks = <&dispcc 0>, <&dispcc 1>;
75 #phy-cells = <0>;
|
| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
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| H A D | phy-qcom-qmp-qserdes-com-v5.h | 10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
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| H A D | phy-qcom-qmp-qserdes-com-v4.h | 10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
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| H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
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| H A D | phy-qcom-qmp-pcs-v3.h | 10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
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| H A D | phy-qcom-qmp-qserdes-com.h | 10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
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| H A D | phy-qcom-qmp-pcs-v4.h | 10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
| H A D | clock-axg.h | 18 #define HHI_GP0_PLL_CNTL 0x40
19 #define HHI_GP0_PLL_CNTL2 0x44
20 #define HHI_GP0_PLL_CNTL3 0x48
21 #define HHI_GP0_PLL_CNTL4 0x4c
22 #define HHI_GP0_PLL_CNTL5 0x50
23 #define HHI_GP0_PLL_STS 0x54
24 #define HHI_GP0_PLL_CNTL1 0x58
25 #define HHI_HIFI_PLL_CNTL 0x80
26 #define HHI_HIFI_PLL_CNTL2 0x84
27 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
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| /openbmc/linux/drivers/clk/meson/ |
| H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
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| H A D | g12a.h | 20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra124/ |
| H A D | gp_padctrl.h | 14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | gp_padctrl.h | 14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra114/ |
| H A D | gp_padctrl.h | 13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
19 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
20 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
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