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Searched +full:0 +full:x18800000 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/arch/mips/pci/
H A Dpci-rc32434.c36 #define PCI_ACCESS_READ 0
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
62 .start = 0x60000000,
63 .end = 0x6FFFFFFF,
72 .start = 0x18800000,
73 .end = 0x188FFFFF,
97 .mem_offset = 0,
98 .io_offset = 0,
105 #define PCI_ENDIAN_FLAG 0
[all …]
H A Dpci-lantiq.c27 #define PCI_CR_FCI_ADDR_MAP0 0x00C0
28 #define PCI_CR_FCI_ADDR_MAP1 0x00C4
29 #define PCI_CR_FCI_ADDR_MAP2 0x00C8
30 #define PCI_CR_FCI_ADDR_MAP3 0x00CC
31 #define PCI_CR_FCI_ADDR_MAP4 0x00D0
32 #define PCI_CR_FCI_ADDR_MAP5 0x00D4
33 #define PCI_CR_FCI_ADDR_MAP6 0x00D8
34 #define PCI_CR_FCI_ADDR_MAP7 0x00DC
35 #define PCI_CR_CLK_CTRL 0x0000
36 #define PCI_CR_PCI_MOD 0x0030
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml109 enum: [0, 1]
271 reg = <0x18800000 0x800000>;
288 iommus = <&anoc2_smmu 0x1900>,
289 <&anoc2_smmu 0x1901>;
298 iommus = <&apps_smmu 0x1c02 0x1>;
308 reg = <0xa000000 0x200000>;
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dmac.h11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define BSSID_CAM_ENT_SIZE 0x08
18 RTW89_DMAC_SEL = 0,
25 RTW89_FWD_DONT_CARE = 0,
41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
53 RTW89_MAC_TAG_NUM_DEF = 0xFE
57 RTW89_MAC_LBC_TMR_8US = 0,
68 RTW89_MAC_LBC_TMR_DEF = 0xFE
72 CPUIO_OP_CMD_GET_1ST_PID = 0,
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dregs.h42 #define MT_MCU_INT_EVENT 0x2108
43 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
48 #define MT_PLE_BASE 0x820c0000
51 #define MT_FL_Q_EMPTY MT_PLE(0x360)
52 #define MT_FL_Q0_CTRL MT_PLE(0x3e0)
53 #define MT_FL_Q2_CTRL MT_PLE(0x3e8)
54 #define MT_FL_Q3_CTRL MT_PLE(0x3ec)
56 #define MT_PLE_FREEPG_CNT MT_PLE(0x380)
57 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
58 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
[all …]
/openbmc/linux/arch/mips/alchemy/devboards/
H A Ddb1200.c35 #define BCSR_INT_IDE 0x0001
36 #define BCSR_INT_ETH 0x0002
37 #define BCSR_INT_PC0 0x0004
38 #define BCSR_INT_PC0STSCHG 0x0008
39 #define BCSR_INT_PC1 0x0010
40 #define BCSR_INT_PC1STSCHG 0x0020
41 #define BCSR_INT_DC 0x0040
42 #define BCSR_INT_FLASHBUSY 0x0080
43 #define BCSR_INT_PC0INSERT 0x0100
44 #define BCSR_INT_PC0EJECT 0x0200
[all …]
H A Ddb1300.c39 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
57 #define DB1300_ETH_PHYS_ADDR 0x19000000
58 #define DB1300_ETH_PHYS_END 0x197fffff
61 #define DB1300_IDE_PHYS_ADDR 0x18800000
66 #define DB1300_NAND_PHYS_ADDR 0x20000000
67 #define DB1300_NAND_PHYS_END 0x20000fff
71 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
72 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
85 /* wake-from-str pins 0-3 */
137 i = &db1300_dev_pins[0]; in db1300_gpio_config()
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8710b.c34 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
35 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
36 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
37 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
38 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
39 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
40 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
41 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
42 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
43 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]
H A Drtl8xxxu_8188f.c34 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20},
35 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
36 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
37 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
38 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
39 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
40 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
41 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
42 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
43 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44},
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dregs.h129 #define MT_MCU_WFDMA0_BASE 0x2000
132 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
135 #define MT_MCU_WFDMA1_BASE 0x3000
139 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
145 #define MT_PLE_BASE 0x820c0000
148 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
153 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
154 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
164 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
166 #define MT_PSE_BASE 0x820c8000
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dmsm8998.dtsi15 qcom,msm-id = <292 0x0>;
25 reg = <0x0 0x80000000 0x0 0x0>;
34 reg = <0x0 0x85800000 0x0 0x600000>;
39 reg = <0x0 0x85e00000 0x0 0x100000>;
44 reg = <0x0 0x86000000 0x0 0x200000>;
49 reg = <0x0 0x86200000 0x0 0x2d00000>;
55 reg = <0x0 0x88f00000 0x0 0x200000>;
63 reg = <0x0 0x8ab00000 0x0 0x700000>;
68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsc8180x.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]