1e57b7901SRyder Lee /* SPDX-License-Identifier: ISC */ 2e57b7901SRyder Lee /* Copyright (C) 2020 MediaTek Inc. */ 3e57b7901SRyder Lee 4e57b7901SRyder Lee #ifndef __MT7915_REGS_H 5e57b7901SRyder Lee #define __MT7915_REGS_H 6e57b7901SRyder Lee 7cd4c314aSBo Jiao /* used to differentiate between generations */ 8cd4c314aSBo Jiao struct mt7915_reg_desc { 9cd4c314aSBo Jiao const u32 *reg_rev; 10cd4c314aSBo Jiao const u32 *offs_rev; 11e351f4f0SLorenzo Bianconi const struct mt76_connac_reg_map *map; 12cd4c314aSBo Jiao u32 map_size; 13cd4c314aSBo Jiao }; 14cd4c314aSBo Jiao 15cd4c314aSBo Jiao enum reg_rev { 16cd4c314aSBo Jiao INT_SOURCE_CSR, 17cd4c314aSBo Jiao INT_MASK_CSR, 18cd4c314aSBo Jiao INT1_SOURCE_CSR, 19cd4c314aSBo Jiao INT1_MASK_CSR, 20cd4c314aSBo Jiao INT_MCU_CMD_SOURCE, 21cd4c314aSBo Jiao INT_MCU_CMD_EVENT, 2299ad32a4SBo Jiao WFDMA0_ADDR, 2399ad32a4SBo Jiao WFDMA0_PCIE1_ADDR, 2499ad32a4SBo Jiao WFDMA_EXT_CSR_ADDR, 2599ad32a4SBo Jiao CBTOP1_PHY_END, 2699ad32a4SBo Jiao INFRA_MCU_ADDR_END, 274dbcb912SRyder Lee FW_ASSERT_STAT_ADDR, 284dbcb912SRyder Lee FW_EXCEPT_TYPE_ADDR, 294dbcb912SRyder Lee FW_EXCEPT_COUNT_ADDR, 304dbcb912SRyder Lee FW_CIRQ_COUNT_ADDR, 314dbcb912SRyder Lee FW_CIRQ_IDX_ADDR, 324dbcb912SRyder Lee FW_CIRQ_LISR_ADDR, 334dbcb912SRyder Lee FW_TASK_ID_ADDR, 344dbcb912SRyder Lee FW_TASK_IDX_ADDR, 354dbcb912SRyder Lee FW_TASK_QID1_ADDR, 364dbcb912SRyder Lee FW_TASK_QID2_ADDR, 374dbcb912SRyder Lee FW_TASK_START_ADDR, 384dbcb912SRyder Lee FW_TASK_END_ADDR, 394dbcb912SRyder Lee FW_TASK_SIZE_ADDR, 404dbcb912SRyder Lee FW_LAST_MSG_ID_ADDR, 414dbcb912SRyder Lee FW_EINT_INFO_ADDR, 424dbcb912SRyder Lee FW_SCHED_INFO_ADDR, 43bdd2ca78SRyder Lee SWDEF_BASE_ADDR, 44eebb7097SLorenzo Bianconi TXQ_WED_RING_BASE, 45eebb7097SLorenzo Bianconi RXQ_WED_RING_BASE, 464f831d18SLorenzo Bianconi RXQ_WED_DATA_RING_BASE, 47cd4c314aSBo Jiao __MT_REG_MAX, 48cd4c314aSBo Jiao }; 49cd4c314aSBo Jiao 50cd4c314aSBo Jiao enum offs_rev { 51cd4c314aSBo Jiao TMAC_CDTR, 52cd4c314aSBo Jiao TMAC_ODTR, 53cd4c314aSBo Jiao TMAC_ATCR, 54cd4c314aSBo Jiao TMAC_TRCR0, 55cd4c314aSBo Jiao TMAC_ICR0, 56cd4c314aSBo Jiao TMAC_ICR1, 57cd4c314aSBo Jiao TMAC_CTCR0, 58cd4c314aSBo Jiao TMAC_TFCR0, 59cd4c314aSBo Jiao MDP_BNRCFR0, 60cd4c314aSBo Jiao MDP_BNRCFR1, 61cd4c314aSBo Jiao ARB_DRNGR0, 62cd4c314aSBo Jiao ARB_SCR, 63cd4c314aSBo Jiao RMAC_MIB_AIRTIME14, 64cd4c314aSBo Jiao AGG_AWSCR0, 65cd4c314aSBo Jiao AGG_PCR0, 66cd4c314aSBo Jiao AGG_ACR0, 6743eaa368SRyder Lee AGG_ACR4, 68cd4c314aSBo Jiao AGG_MRCR, 69cd4c314aSBo Jiao AGG_ATCR1, 70cd4c314aSBo Jiao AGG_ATCR3, 71cd4c314aSBo Jiao LPON_UTTR0, 72cd4c314aSBo Jiao LPON_UTTR1, 73988845c9SFelix Fietkau LPON_FRCR, 74cd4c314aSBo Jiao MIB_SDR3, 75cd4c314aSBo Jiao MIB_SDR4, 76cd4c314aSBo Jiao MIB_SDR5, 77cd4c314aSBo Jiao MIB_SDR7, 78cd4c314aSBo Jiao MIB_SDR8, 79cd4c314aSBo Jiao MIB_SDR9, 80cd4c314aSBo Jiao MIB_SDR10, 81cd4c314aSBo Jiao MIB_SDR11, 82cd4c314aSBo Jiao MIB_SDR12, 83cd4c314aSBo Jiao MIB_SDR13, 84cd4c314aSBo Jiao MIB_SDR14, 85cd4c314aSBo Jiao MIB_SDR15, 86cd4c314aSBo Jiao MIB_SDR16, 87cd4c314aSBo Jiao MIB_SDR17, 88cd4c314aSBo Jiao MIB_SDR18, 89cd4c314aSBo Jiao MIB_SDR19, 90cd4c314aSBo Jiao MIB_SDR20, 91cd4c314aSBo Jiao MIB_SDR21, 92cd4c314aSBo Jiao MIB_SDR22, 93cd4c314aSBo Jiao MIB_SDR23, 94cd4c314aSBo Jiao MIB_SDR24, 95cd4c314aSBo Jiao MIB_SDR25, 96cd4c314aSBo Jiao MIB_SDR27, 97cd4c314aSBo Jiao MIB_SDR28, 98cd4c314aSBo Jiao MIB_SDR29, 99cd4c314aSBo Jiao MIB_SDRVEC, 100cd4c314aSBo Jiao MIB_SDR31, 101cd4c314aSBo Jiao MIB_SDR32, 102cd4c314aSBo Jiao MIB_SDRMUBF, 103cd4c314aSBo Jiao MIB_DR8, 104cd4c314aSBo Jiao MIB_DR9, 105cd4c314aSBo Jiao MIB_DR11, 106cd4c314aSBo Jiao MIB_MB_SDR0, 107cd4c314aSBo Jiao MIB_MB_SDR1, 108cd4c314aSBo Jiao TX_AGG_CNT, 109cd4c314aSBo Jiao TX_AGG_CNT2, 110cd4c314aSBo Jiao MIB_ARNG, 111cd4c314aSBo Jiao WTBLON_TOP_WDUCR, 112cd4c314aSBo Jiao WTBL_UPDATE, 113cd4c314aSBo Jiao PLE_FL_Q_EMPTY, 114cd4c314aSBo Jiao PLE_FL_Q_CTRL, 115cd4c314aSBo Jiao PLE_AC_QEMPTY, 116cd4c314aSBo Jiao PLE_FREEPG_CNT, 117cd4c314aSBo Jiao PLE_FREEPG_HEAD_TAIL, 118cd4c314aSBo Jiao PLE_PG_HIF_GROUP, 119cd4c314aSBo Jiao PLE_HIF_PG_INFO, 120cd4c314aSBo Jiao AC_OFFSET, 121bd1407edSShayne Chen ETBF_PAR_RPT0, 122cd4c314aSBo Jiao __MT_OFFS_MAX, 123cd4c314aSBo Jiao }; 124cd4c314aSBo Jiao 125cd4c314aSBo Jiao #define __REG(id) (dev->reg.reg_rev[(id)]) 126cd4c314aSBo Jiao #define __OFFS(id) (dev->reg.offs_rev[(id)]) 127cd4c314aSBo Jiao 128e07419a7SRyder Lee /* MCU WFDMA0 */ 129e07419a7SRyder Lee #define MT_MCU_WFDMA0_BASE 0x2000 130e07419a7SRyder Lee #define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs)) 131cd4c314aSBo Jiao 132e07419a7SRyder Lee #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120) 133e07419a7SRyder Lee 134e57b7901SRyder Lee /* MCU WFDMA1 */ 135e57b7901SRyder Lee #define MT_MCU_WFDMA1_BASE 0x3000 136e57b7901SRyder Lee #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 137e57b7901SRyder Lee 138cd4c314aSBo Jiao #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) 139e57b7901SRyder Lee #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 140e57b7901SRyder Lee #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 141e57b7901SRyder Lee #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 142e57b7901SRyder Lee #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 143e57b7901SRyder Lee 144cd4c314aSBo Jiao /* PLE */ 145cd4c314aSBo Jiao #define MT_PLE_BASE 0x820c0000 146e57b7901SRyder Lee #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 147e57b7901SRyder Lee 148943e4fb9SRyder Lee #define MT_PLE_HOST_RPT0 MT_PLE(0x030) 149943e4fb9SRyder Lee #define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3) 150943e4fb9SRyder Lee 151cd4c314aSBo Jiao #define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY)) 152cd4c314aSBo Jiao #define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL)) 153cd4c314aSBo Jiao #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8) 154cd4c314aSBo Jiao #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc) 155e57b7901SRyder Lee 156cd4c314aSBo Jiao #define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT)) 157cd4c314aSBo Jiao #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL)) 158cd4c314aSBo Jiao #define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP)) 159cd4c314aSBo Jiao #define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO)) 160cd4c314aSBo Jiao 161cd4c314aSBo Jiao #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \ 162cd4c314aSBo Jiao __OFFS(AC_OFFSET) * \ 163cd4c314aSBo Jiao (ac) + ((n) << 2)) 164e57b7901SRyder Lee #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 165e57b7901SRyder Lee 166cd4c314aSBo Jiao #define MT_PSE_BASE 0x820c8000 167776ec4e7SRyder Lee #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) 168776ec4e7SRyder Lee 169cd4c314aSBo Jiao /* WF MDP TOP */ 170cd4c314aSBo Jiao #define MT_MDP_BASE 0x820cd000 171e57b7901SRyder Lee #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 172e57b7901SRyder Lee 173e57b7901SRyder Lee #define MT_MDP_DCR0 MT_MDP(0x000) 174e57b7901SRyder Lee #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 175e57b7901SRyder Lee 176e57b7901SRyder Lee #define MT_MDP_DCR1 MT_MDP(0x004) 177e57b7901SRyder Lee #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 178e57b7901SRyder Lee 17946f6adbfSBo Jiao #define MT_MDP_DCR2 MT_MDP(0x0e8) 18046f6adbfSBo Jiao #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 18146f6adbfSBo Jiao 182cd4c314aSBo Jiao #define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \ 183cd4c314aSBo Jiao ((_band) << 8)) 184e57b7901SRyder Lee #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 185e57b7901SRyder Lee #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 186e57b7901SRyder Lee #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 187e57b7901SRyder Lee 188cd4c314aSBo Jiao #define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \ 189cd4c314aSBo Jiao ((_band) << 8)) 190e57b7901SRyder Lee #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 191e57b7901SRyder Lee #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 192e57b7901SRyder Lee #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 193e57b7901SRyder Lee #define MT_MDP_TO_HIF 0 194e57b7901SRyder Lee #define MT_MDP_TO_WM 1 195e57b7901SRyder Lee 196b4c268caSRyder Lee /* TRB: band 0(0x820e1000), band 1(0x820f1000) */ 197b4c268caSRyder Lee #define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000) 198b4c268caSRyder Lee #define MT_WF_TRB(_band, ofs) (MT_WF_TRB_BASE(_band) + (ofs)) 199b4c268caSRyder Lee 200b4c268caSRyder Lee #define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c) 201b4c268caSRyder Lee #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16) 202b4c268caSRyder Lee #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0) 203b4c268caSRyder Lee 204cd4c314aSBo Jiao /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ 205cd4c314aSBo Jiao #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 206e57b7901SRyder Lee #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 207e57b7901SRyder Lee 208aadf0953SShayne Chen #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 2090421bf80SMeiChia Chiu #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 210aadf0953SShayne Chen #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 211aadf0953SShayne Chen 212cd4c314aSBo Jiao #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) 213cd4c314aSBo Jiao #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) 214e57b7901SRyder Lee #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 215e57b7901SRyder Lee #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 216e57b7901SRyder Lee 217cd4c314aSBo Jiao #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR)) 218c2d3b192SShayne Chen #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) 219c2d3b192SShayne Chen 220cd4c314aSBo Jiao #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0)) 221c2d3b192SShayne Chen #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) 222c2d3b192SShayne Chen #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) 223c2d3b192SShayne Chen 224cd4c314aSBo Jiao #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0)) 2259aac2969SRyder Lee #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 226e57b7901SRyder Lee #define MT_IFS_RIFS GENMASK(14, 10) 227e57b7901SRyder Lee #define MT_IFS_SIFS GENMASK(22, 16) 228e57b7901SRyder Lee #define MT_IFS_SLOT GENMASK(30, 24) 229e57b7901SRyder Lee 230cd4c314aSBo Jiao #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1)) 2319aac2969SRyder Lee #define MT_IFS_EIFS_CCK GENMASK(8, 0) 2329aac2969SRyder Lee 233cd4c314aSBo Jiao #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0)) 234e57b7901SRyder Lee #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 235e57b7901SRyder Lee #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 236e57b7901SRyder Lee #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 237e57b7901SRyder Lee 238cd4c314aSBo Jiao #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0)) 239aadf0953SShayne Chen 240cd4c314aSBo Jiao /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ 241cd4c314aSBo Jiao #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 2424c430774SLorenzo Bianconi #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 243e57b7901SRyder Lee 2444c430774SLorenzo Bianconi #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 245e57b7901SRyder Lee #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 2465205071aSRyder Lee #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 247e57b7901SRyder Lee 248a71b648eSRyder Lee /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ 249a71b648eSRyder Lee #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000) 250a71b648eSRyder Lee #define MT_WTBLOFF_TOP(_band, ofs) (MT_WTBLOFF_TOP_BASE(_band) + (ofs)) 251a71b648eSRyder Lee 252a71b648eSRyder Lee #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008) 253a71b648eSRyder Lee #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30) 254a71b648eSRyder Lee #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24) 255a71b648eSRyder Lee 256cd4c314aSBo Jiao /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ 257cd4c314aSBo Jiao #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 258babdad50SRyder Lee #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 259babdad50SRyder Lee 260babdad50SRyder Lee #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) 261babdad50SRyder Lee #define MT_ETBF_TX_FB_CPL GENMASK(31, 16) 262babdad50SRyder Lee #define MT_ETBF_TX_FB_TRI GENMASK(15, 0) 263babdad50SRyder Lee 264bd1407edSShayne Chen #define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0)) 265bd1407edSShayne Chen #define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6) 266bd1407edSShayne Chen #define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3) 267bd1407edSShayne Chen #define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0) 268b70946ceSRyder Lee 269babdad50SRyder Lee #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) 270babdad50SRyder Lee #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 271babdad50SRyder Lee #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 272babdad50SRyder Lee 273babdad50SRyder Lee #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) 274babdad50SRyder Lee #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 275babdad50SRyder Lee #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 276babdad50SRyder Lee #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 277babdad50SRyder Lee #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 278babdad50SRyder Lee 279cd4c314aSBo Jiao /* LPON: band 0(0x820eb000), band 1(0x820fb000) */ 280cd4c314aSBo Jiao #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 28132add88fSRyder Lee #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 28232add88fSRyder Lee 283cd4c314aSBo Jiao #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0)) 284cd4c314aSBo Jiao #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1)) 285988845c9SFelix Fietkau #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR)) 28632add88fSRyder Lee 287cd4c314aSBo Jiao #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 288cd4c314aSBo Jiao (((n) * 4) << 1)) 289cd4c314aSBo Jiao #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 290cd4c314aSBo Jiao (((n) * 4) << 4)) 29132add88fSRyder Lee #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 29232add88fSRyder Lee #define MT_LPON_TCR_SW_WRITE BIT(0) 29316073134SRyder Lee #define MT_LPON_TCR_SW_ADJUST BIT(1) 29416073134SRyder Lee #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 29532add88fSRyder Lee 296cd4c314aSBo Jiao /* MIB: band 0(0x820ed000), band 1(0x820fd000) */ 297a90f2115SBen Greear /* These counters are (mostly?) clear-on-read. So, some should not 298a90f2115SBen Greear * be read at all in case firmware is already reading them. These 299a90f2115SBen Greear * are commented with 'DNR' below. The DNR stats will be read by querying 300a90f2115SBen Greear * the firmware API for the appropriate message. For counters the driver 301a90f2115SBen Greear * does read, the driver should accumulate the counters. 302a90f2115SBen Greear */ 303cd4c314aSBo Jiao #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 304e57b7901SRyder Lee #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 305e57b7901SRyder Lee 306a90f2115SBen Greear #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010) 307a90f2115SBen Greear #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0) 308a90f2115SBen Greear 309cd4c314aSBo Jiao #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3)) 310e57b7901SRyder Lee #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 311cd4c314aSBo Jiao #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16) 312e57b7901SRyder Lee 313cd4c314aSBo Jiao #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4)) 314a90f2115SBen Greear #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) 315a90f2115SBen Greear 316a90f2115SBen Greear /* rx mpdu counter, full 32 bits */ 317cd4c314aSBo Jiao #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5)) 318a90f2115SBen Greear 319a90f2115SBen Greear #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 320a90f2115SBen Greear #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 321a90f2115SBen Greear 322cd4c314aSBo Jiao #define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7)) 323a90f2115SBen Greear #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0) 324a90f2115SBen Greear 325cd4c314aSBo Jiao #define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8)) 326a90f2115SBen Greear #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0) 327a90f2115SBen Greear 328a90f2115SBen Greear /* aka CCA_NAV_TX_TIME */ 329cd4c314aSBo Jiao #define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9)) 330a90f2115SBen Greear #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0) 331a90f2115SBen Greear 3323685727cSRyder Lee #define MT_MIB_SDR10(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10)) 333a90f2115SBen Greear #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0) 334cd4c314aSBo Jiao #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0) 335a90f2115SBen Greear 336cd4c314aSBo Jiao #define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11)) 337a90f2115SBen Greear #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0) 338a90f2115SBen Greear 339a90f2115SBen Greear /* tx ampdu cnt, full 32 bits */ 340cd4c314aSBo Jiao #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12)) 341a90f2115SBen Greear 342cd4c314aSBo Jiao #define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13)) 343a90f2115SBen Greear #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0) 344a90f2115SBen Greear 345a90f2115SBen Greear /* counts all mpdus in ampdu, regardless of success */ 346cd4c314aSBo Jiao #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14)) 347a90f2115SBen Greear #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0) 348cd4c314aSBo Jiao #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0) 349a90f2115SBen Greear 350a90f2115SBen Greear /* counts all successfully tx'd mpdus in ampdu */ 351cd4c314aSBo Jiao #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15)) 352a90f2115SBen Greear #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0) 353cd4c314aSBo Jiao #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0) 354a90f2115SBen Greear 355a90f2115SBen Greear /* in units of 'us' */ 3563685727cSRyder Lee #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16)) 357a90f2115SBen Greear #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 358a90f2115SBen Greear 3593685727cSRyder Lee #define MT_MIB_SDR17(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17)) 360a90f2115SBen Greear #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 361a90f2115SBen Greear 362cd4c314aSBo Jiao #define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18)) 363a90f2115SBen Greear #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0) 364a90f2115SBen Greear 365a90f2115SBen Greear /* units are us */ 3663685727cSRyder Lee #define MT_MIB_SDR19(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19)) 367a90f2115SBen Greear #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0) 368a90f2115SBen Greear 3693685727cSRyder Lee #define MT_MIB_SDR20(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20)) 370a90f2115SBen Greear #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0) 371a90f2115SBen Greear 3723685727cSRyder Lee #define MT_MIB_SDR21(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21)) 3733685727cSRyder Lee #define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0) 374a90f2115SBen Greear 375a90f2115SBen Greear /* rx ampdu count, 32-bit */ 376cd4c314aSBo Jiao #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22)) 377a90f2115SBen Greear 378a90f2115SBen Greear /* rx ampdu bytes count, 32-bit */ 379cd4c314aSBo Jiao #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23)) 380a90f2115SBen Greear 381a90f2115SBen Greear /* rx ampdu valid subframe count */ 382cd4c314aSBo Jiao #define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24)) 383a90f2115SBen Greear #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0) 384cd4c314aSBo Jiao #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0) 385a90f2115SBen Greear 386a90f2115SBen Greear /* rx ampdu valid subframe bytes count, 32bits */ 387cd4c314aSBo Jiao #define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25)) 388a90f2115SBen Greear 389a90f2115SBen Greear /* remaining windows protected stats */ 390cd4c314aSBo Jiao #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27)) 391a90f2115SBen Greear #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0) 392a90f2115SBen Greear 393cd4c314aSBo Jiao #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28)) 394a90f2115SBen Greear #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0) 395a90f2115SBen Greear 396cd4c314aSBo Jiao #define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29)) 397a90f2115SBen Greear #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0) 398cd4c314aSBo Jiao #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0) 399a90f2115SBen Greear 400cd4c314aSBo Jiao #define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC)) 401a90f2115SBen Greear #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0) 402cd4c314aSBo Jiao #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16) 403a90f2115SBen Greear 404a90f2115SBen Greear /* rx blockack count, 32 bits */ 405cd4c314aSBo Jiao #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31)) 406a90f2115SBen Greear 407cd4c314aSBo Jiao #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32)) 408bd1407edSShayne Chen #define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0) 409bd1407edSShayne Chen #define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16) 410a90f2115SBen Greear 411cd4c314aSBo Jiao #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088) 412bd1407edSShayne Chen #define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0) 413a90f2115SBen Greear 414cd4c314aSBo Jiao #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF)) 415f68e6a1fSRyder Lee #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 416f68e6a1fSRyder Lee 417a90f2115SBen Greear /* 36, 37 both DNR */ 418a90f2115SBen Greear 419cd4c314aSBo Jiao #define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8)) 420cd4c314aSBo Jiao #define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9)) 421cd4c314aSBo Jiao #define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11)) 422babdad50SRyder Lee 423cd4c314aSBo Jiao #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n)) 424e57b7901SRyder Lee #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 425e57b7901SRyder Lee #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 426e57b7901SRyder Lee 427cd4c314aSBo Jiao #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n)) 428e57b7901SRyder Lee #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 429e57b7901SRyder Lee #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 430e57b7901SRyder Lee 431cd4c314aSBo Jiao #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n)) 432cd4c314aSBo Jiao #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n)) 433cd4c314aSBo Jiao 434cd4c314aSBo Jiao #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \ 435cd4c314aSBo Jiao ((n) << 2)) 436cd4c314aSBo Jiao #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \ 437cd4c314aSBo Jiao ((n) << 2)) 438cd4c314aSBo Jiao #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \ 439cd4c314aSBo Jiao ((n) << 2)) 440e57b7901SRyder Lee #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 441e57b7901SRyder Lee 442bd1407edSShayne Chen #define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0) 443bd1407edSShayne Chen #define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0) 444bd1407edSShayne Chen #define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16) 445bd1407edSShayne Chen 446bd1407edSShayne Chen #define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4) 447bd1407edSShayne Chen #define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0) 448bd1407edSShayne Chen 449bd1407edSShayne Chen #define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8) 450bd1407edSShayne Chen #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0) 451bd1407edSShayne Chen 452bd1407edSShayne Chen #define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc) 453bd1407edSShayne Chen #define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0) 454bd1407edSShayne Chen 455cd4c314aSBo Jiao /* WTBLON TOP */ 456cd4c314aSBo Jiao #define MT_WTBLON_TOP_BASE 0x820d4000 457e57b7901SRyder Lee #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 458cd4c314aSBo Jiao #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR)) 459e57b7901SRyder Lee #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 460e57b7901SRyder Lee 461cd4c314aSBo Jiao #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 462e57b7901SRyder Lee #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 463e57b7901SRyder Lee #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 464e57b7901SRyder Lee #define MT_WTBL_UPDATE_BUSY BIT(31) 465e57b7901SRyder Lee 466cd4c314aSBo Jiao /* WTBL */ 467cd4c314aSBo Jiao #define MT_WTBL_BASE 0x820d8000 468e57b7901SRyder Lee #define MT_WTBL_LMAC_ID GENMASK(14, 8) 469e57b7901SRyder Lee #define MT_WTBL_LMAC_DW GENMASK(7, 2) 470e57b7901SRyder Lee #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 471e57b7901SRyder Lee FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 472e57b7901SRyder Lee FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 473e57b7901SRyder Lee 474cd4c314aSBo Jiao /* AGG: band 0(0x820e2000), band 1(0x820f2000) */ 475cd4c314aSBo Jiao #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 476e57b7901SRyder Lee #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 477e57b7901SRyder Lee 478cd4c314aSBo Jiao #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \ 479cd4c314aSBo Jiao (_n) * 4)) 480cd4c314aSBo Jiao #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \ 481cd4c314aSBo Jiao (_n) * 4)) 482aadf0953SShayne Chen #define MT_AGG_PCR0_MM_PROT BIT(0) 483aadf0953SShayne Chen #define MT_AGG_PCR0_GF_PROT BIT(1) 484aadf0953SShayne Chen #define MT_AGG_PCR0_BW20_PROT BIT(2) 485aadf0953SShayne Chen #define MT_AGG_PCR0_BW40_PROT BIT(4) 486aadf0953SShayne Chen #define MT_AGG_PCR0_BW80_PROT BIT(6) 487aadf0953SShayne Chen #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 488aadf0953SShayne Chen #define MT_AGG_PCR0_VHT_PROT BIT(13) 489aadf0953SShayne Chen #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 490aadf0953SShayne Chen 491aadf0953SShayne Chen #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 492aadf0953SShayne Chen #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 493aadf0953SShayne Chen 494cd4c314aSBo Jiao #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) 495e57b7901SRyder Lee #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 496e57b7901SRyder Lee #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 497e57b7901SRyder Lee 49843eaa368SRyder Lee #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR4)) 49943eaa368SRyder Lee #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 50043eaa368SRyder Lee 501cd4c314aSBo Jiao #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR)) 502aadf0953SShayne Chen #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 503aadf0953SShayne Chen #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 504aadf0953SShayne Chen #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 505aadf0953SShayne Chen #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 506aadf0953SShayne Chen 507cd4c314aSBo Jiao #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1)) 508cd4c314aSBo Jiao #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3)) 509aadf0953SShayne Chen 510cd4c314aSBo Jiao /* ARB: band 0(0x820e3000), band 1(0x820f3000) */ 511cd4c314aSBo Jiao #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 512e57b7901SRyder Lee #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 513e57b7901SRyder Lee 514cd4c314aSBo Jiao #define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR)) 515e57b7901SRyder Lee #define MT_ARB_SCR_TX_DISABLE BIT(8) 516e57b7901SRyder Lee #define MT_ARB_SCR_RX_DISABLE BIT(9) 517e57b7901SRyder Lee 518cd4c314aSBo Jiao #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \ 519cd4c314aSBo Jiao (_n) * 4)) 520aadf0953SShayne Chen 521cd4c314aSBo Jiao /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ 522cd4c314aSBo Jiao #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 523e57b7901SRyder Lee #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 524e57b7901SRyder Lee 525e57b7901SRyder Lee #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 526e57b7901SRyder Lee #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 527e57b7901SRyder Lee #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 528e57b7901SRyder Lee #define MT_WF_RFCR_DROP_VERSION BIT(3) 529e57b7901SRyder Lee #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 530e57b7901SRyder Lee #define MT_WF_RFCR_DROP_MCAST BIT(5) 531e57b7901SRyder Lee #define MT_WF_RFCR_DROP_BCAST BIT(6) 532e57b7901SRyder Lee #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 533e57b7901SRyder Lee #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 534e57b7901SRyder Lee #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 535e57b7901SRyder Lee #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 536e57b7901SRyder Lee #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 537e57b7901SRyder Lee #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 538e57b7901SRyder Lee #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 539e57b7901SRyder Lee #define MT_WF_RFCR_DROP_CTS BIT(14) 540e57b7901SRyder Lee #define MT_WF_RFCR_DROP_RTS BIT(15) 541e57b7901SRyder Lee #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 542e57b7901SRyder Lee #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 543e57b7901SRyder Lee #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 544e57b7901SRyder Lee #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 545e57b7901SRyder Lee #define MT_WF_RFCR_DROP_NDPA BIT(20) 546e57b7901SRyder Lee #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 547e57b7901SRyder Lee 548e57b7901SRyder Lee #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 549e57b7901SRyder Lee #define MT_WF_RFCR1_DROP_ACK BIT(4) 550e57b7901SRyder Lee #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 551e57b7901SRyder Lee #define MT_WF_RFCR1_DROP_BA BIT(6) 552e57b7901SRyder Lee #define MT_WF_RFCR1_DROP_CFEND BIT(7) 553e57b7901SRyder Lee #define MT_WF_RFCR1_DROP_CFACK BIT(8) 554e57b7901SRyder Lee 555b0bfa005SRyder Lee #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x02e0) 556b0bfa005SRyder Lee #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 557b0bfa005SRyder Lee 55865430028SRyder Lee #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 559e57b7901SRyder Lee #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 560b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 561b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 562b0bfa005SRyder Lee 563b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 564b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 565b0bfa005SRyder Lee 566b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 567b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 568b0bfa005SRyder Lee 569b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 570b0bfa005SRyder Lee #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 571e57b7901SRyder Lee 572e57b7901SRyder Lee /* WFDMA0 */ 57399ad32a4SBo Jiao #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR) 574e57b7901SRyder Lee #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 575e57b7901SRyder Lee 576e57b7901SRyder Lee #define MT_WFDMA0_RST MT_WFDMA0(0x100) 577e57b7901SRyder Lee #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 578e57b7901SRyder Lee #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 579e57b7901SRyder Lee 580e57b7901SRyder Lee #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 581e57b7901SRyder Lee #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 582e57b7901SRyder Lee #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 583e57b7901SRyder Lee #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 584e57b7901SRyder Lee 5858a55712dSBo Jiao #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 5868a55712dSBo Jiao 587e57b7901SRyder Lee #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 588e57b7901SRyder Lee #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 589e57b7901SRyder Lee #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 590aa79fe87SBo Jiao #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 591aa79fe87SBo Jiao #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 592aa79fe87SBo Jiao #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 593e57b7901SRyder Lee 594e57b7901SRyder Lee #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 5954f831d18SLorenzo Bianconi 5964f831d18SLorenzo Bianconi #define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0) 5974f831d18SLorenzo Bianconi #define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10) 5984f831d18SLorenzo Bianconi 599e57b7901SRyder Lee #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 600aa79fe87SBo Jiao #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 601aa79fe87SBo Jiao #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 6024f831d18SLorenzo Bianconi #define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208) 603e57b7901SRyder Lee 604e57b7901SRyder Lee /* WFDMA1 */ 605e57b7901SRyder Lee #define MT_WFDMA1_BASE 0xd5000 606e57b7901SRyder Lee #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) 607e57b7901SRyder Lee 608e57b7901SRyder Lee #define MT_WFDMA1_RST MT_WFDMA1(0x100) 609e57b7901SRyder Lee #define MT_WFDMA1_RST_LOGIC_RST BIT(4) 610e57b7901SRyder Lee #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) 611e57b7901SRyder Lee 612e57b7901SRyder Lee #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) 613e57b7901SRyder Lee #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) 614e57b7901SRyder Lee #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) 615e57b7901SRyder Lee #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) 616e57b7901SRyder Lee 617e57b7901SRyder Lee #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) 618e57b7901SRyder Lee #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) 619e57b7901SRyder Lee #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) 620e57b7901SRyder Lee #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) 621e57b7901SRyder Lee #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) 622aa79fe87SBo Jiao #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 623e57b7901SRyder Lee 624e57b7901SRyder Lee #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) 625e57b7901SRyder Lee #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) 626e57b7901SRyder Lee 627e57b7901SRyder Lee /* WFDMA CSR */ 62899ad32a4SBo Jiao #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR) 629f68d6762SFelix Fietkau #define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000 630e57b7901SRyder Lee #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 631f68d6762SFelix Fietkau #define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs)) 632e57b7901SRyder Lee 633f68d6762SFelix Fietkau #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30) 6349093cfffSFelix Fietkau #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 635f68d6762SFelix Fietkau #define MT_WFDMA_HOST_CONFIG_WED BIT(1) 6369093cfffSFelix Fietkau 637f68d6762SFelix Fietkau #define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34) 638f68d6762SFelix Fietkau #define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0) 639f68d6762SFelix Fietkau #define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) 640f68d6762SFelix Fietkau #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) 641f68d6762SFelix Fietkau 642f68d6762SFelix Fietkau #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) 643e57b7901SRyder Lee #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 644e57b7901SRyder Lee 645cd4c314aSBo Jiao #define MT_PCIE_RECOG_ID 0xd7090 6469093cfffSFelix Fietkau #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 6479093cfffSFelix Fietkau #define MT_PCIE_RECOG_ID_SEM BIT(31) 6489093cfffSFelix Fietkau 649b7ebf46eSLorenzo Bianconi #define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200) 650f68d6762SFelix Fietkau #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204) 651f68d6762SFelix Fietkau 652f68d6762SFelix Fietkau #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300) 653f68d6762SFelix Fietkau #define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400) 654f68d6762SFelix Fietkau 655e57b7901SRyder Lee /* WFDMA0 PCIE1 */ 65699ad32a4SBo Jiao #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR) 657e57b7901SRyder Lee #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 658e57b7901SRyder Lee 659e57b7901SRyder Lee #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 660e57b7901SRyder Lee #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 661e57b7901SRyder Lee #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 662e57b7901SRyder Lee #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 663e57b7901SRyder Lee 664e57b7901SRyder Lee /* WFDMA1 PCIE1 */ 665e57b7901SRyder Lee #define MT_WFDMA1_PCIE1_BASE 0xd9000 666cd4c314aSBo Jiao #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs)) 667e57b7901SRyder Lee 668e57b7901SRyder Lee #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) 669e57b7901SRyder Lee #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 670e57b7901SRyder Lee #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 671e57b7901SRyder Lee #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 672e57b7901SRyder Lee 673cd4c314aSBo Jiao /* WFDMA COMMON */ 674cd4c314aSBo Jiao #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 675fc8f841bSLorenzo Bianconi #define __TXQ(q) (__RXQ(q) + MT_RXQ_BAND2) 676cd4c314aSBo Jiao 677cd4c314aSBo Jiao #define MT_Q_ID(q) (dev->q_id[(q)]) 678cd4c314aSBo Jiao #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \ 679cd4c314aSBo Jiao MT_WFDMA1_BASE : MT_WFDMA0_BASE) 680cd4c314aSBo Jiao 681cd4c314aSBo Jiao #define MT_MCUQ_ID(q) MT_Q_ID(q) 682cd4c314aSBo Jiao #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 683cd4c314aSBo Jiao #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 684cd4c314aSBo Jiao 685cd4c314aSBo Jiao #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 686cd4c314aSBo Jiao #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 687cd4c314aSBo Jiao #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 688cd4c314aSBo Jiao 689cd4c314aSBo Jiao #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 690cd4c314aSBo Jiao MT_MCUQ_ID(q)* 0x4) 691fc8f841bSLorenzo Bianconi #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 692cd4c314aSBo Jiao MT_RXQ_ID(q)* 0x4) 693cd4c314aSBo Jiao #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 694cd4c314aSBo Jiao MT_TXQ_ID(q)* 0x4) 695cd4c314aSBo Jiao 696eebb7097SLorenzo Bianconi #define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE) 697eebb7097SLorenzo Bianconi #define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE) 6984f831d18SLorenzo Bianconi #define MT_RXQ_WED_DATA_RING_BASE __REG(RXQ_WED_DATA_RING_BASE) 699b7ebf46eSLorenzo Bianconi 700cd4c314aSBo Jiao #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) 701cd4c314aSBo Jiao #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) 702cd4c314aSBo Jiao 703cd4c314aSBo Jiao #define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR) 704cd4c314aSBo Jiao #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) 705cd4c314aSBo Jiao 706cd4c314aSBo Jiao #define MT_INT_RX_DONE_BAND0 BIT(16) 707cd4c314aSBo Jiao #define MT_INT_RX_DONE_BAND1 BIT(17) 708cd4c314aSBo Jiao #define MT_INT_RX_DONE_WM BIT(0) 709cd4c314aSBo Jiao #define MT_INT_RX_DONE_WA BIT(1) 710aa79fe87SBo Jiao #define MT_INT_RX_DONE_WA_MAIN BIT(1) 711cd4c314aSBo Jiao #define MT_INT_RX_DONE_WA_EXT BIT(2) 712cd4c314aSBo Jiao #define MT_INT_MCU_CMD BIT(29) 713cd4c314aSBo Jiao #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22) 714cd4c314aSBo Jiao #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23) 715aa79fe87SBo Jiao #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) 716cd4c314aSBo Jiao #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) 717cd4c314aSBo Jiao 718eebb7097SLorenzo Bianconi #define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18) 719eebb7097SLorenzo Bianconi #define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19) 720eebb7097SLorenzo Bianconi #define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1) 721eebb7097SLorenzo Bianconi #define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17) 722eebb7097SLorenzo Bianconi 723cd4c314aSBo Jiao #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 724cd4c314aSBo Jiao #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 725cd4c314aSBo Jiao 726cd4c314aSBo Jiao #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 727cd4c314aSBo Jiao MT_INT_RX(MT_RXQ_MCU_WA)) 728cd4c314aSBo Jiao 729cd4c314aSBo Jiao #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 730aa79fe87SBo Jiao MT_INT_RX(MT_RXQ_MAIN_WA)) 731cd4c314aSBo Jiao 732fc8f841bSLorenzo Bianconi #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 733fc8f841bSLorenzo Bianconi MT_INT_RX(MT_RXQ_BAND1_WA) | \ 734aa79fe87SBo Jiao MT_INT_RX(MT_RXQ_MAIN_WA)) 735cd4c314aSBo Jiao 736cd4c314aSBo Jiao #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 737cd4c314aSBo Jiao MT_INT_BAND0_RX_DONE | \ 738cd4c314aSBo Jiao MT_INT_BAND1_RX_DONE) 739cd4c314aSBo Jiao 740cd4c314aSBo Jiao #define MT_INT_TX_DONE_FWDL BIT(26) 741cd4c314aSBo Jiao #define MT_INT_TX_DONE_MCU_WM BIT(27) 742cd4c314aSBo Jiao #define MT_INT_TX_DONE_MCU_WA BIT(15) 743cd4c314aSBo Jiao #define MT_INT_TX_DONE_BAND0 BIT(30) 744cd4c314aSBo Jiao #define MT_INT_TX_DONE_BAND1 BIT(31) 745cd4c314aSBo Jiao #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) 746eebb7097SLorenzo Bianconi #define MT_INT_WED_TX_DONE_BAND0 BIT(4) 747eebb7097SLorenzo Bianconi #define MT_INT_WED_TX_DONE_BAND1 BIT(5) 748cd4c314aSBo Jiao 749cd4c314aSBo Jiao #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 750cd4c314aSBo Jiao MT_INT_TX_MCU(MT_MCUQ_WM) | \ 751cd4c314aSBo Jiao MT_INT_TX_MCU(MT_MCUQ_FWDL)) 752cd4c314aSBo Jiao 753cd4c314aSBo Jiao #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) 754cd4c314aSBo Jiao #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 755cd4c314aSBo Jiao #define MT_MCU_CMD_STOP_DMA BIT(2) 756cd4c314aSBo Jiao #define MT_MCU_CMD_RESET_DONE BIT(3) 757cd4c314aSBo Jiao #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 758cd4c314aSBo Jiao #define MT_MCU_CMD_NORMAL_STATE BIT(5) 759cd4c314aSBo Jiao #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 760cd4c314aSBo Jiao 761b662b71aSRyder Lee #define MT_MCU_CMD_WA_WDT BIT(31) 762b662b71aSRyder Lee #define MT_MCU_CMD_WM_WDT BIT(30) 7638a55712dSBo Jiao #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 7648a55712dSBo Jiao 765cd4c314aSBo Jiao /* TOP RGU */ 766cd4c314aSBo Jiao #define MT_TOP_RGU_BASE 0x18000000 767e07419a7SRyder Lee #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0)) 768e07419a7SRyder Lee #define MT_TOP_PWR_KEY (0x5746 << 16) 769e07419a7SRyder Lee #define MT_TOP_PWR_SW_RST BIT(0) 770e07419a7SRyder Lee #define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2) 771e07419a7SRyder Lee #define MT_TOP_PWR_HW_CTRL BIT(4) 772e07419a7SRyder Lee #define MT_TOP_PWR_PWR_ON BIT(7) 773e07419a7SRyder Lee 77499ad32a4SBo Jiao #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050) 77599ad32a4SBo Jiao #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054) 77699ad32a4SBo Jiao #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010) 77799ad32a4SBo Jiao #define MT_TOP_PWR_EN_MASK BIT(7) 77899ad32a4SBo Jiao #define MT_TOP_PWR_ACK_MASK BIT(6) 77999ad32a4SBo Jiao #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16) 78099ad32a4SBo Jiao 78199ad32a4SBo Jiao #define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120) 78299ad32a4SBo Jiao #define MT7986_TOP_WM_RESET_MASK BIT(0) 78399ad32a4SBo Jiao 784cd4c314aSBo Jiao /* l1/l2 remap */ 785cd4c314aSBo Jiao #define MT_HIF_REMAP_L1 0xf11ac 786cd4c314aSBo Jiao #define MT_HIF_REMAP_L1_MT7916 0xfe260 787e57b7901SRyder Lee #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 788e57b7901SRyder Lee #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 789e57b7901SRyder Lee #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 790e57b7901SRyder Lee #define MT_HIF_REMAP_BASE_L1 0xe0000 791e57b7901SRyder Lee 792cd4c314aSBo Jiao #define MT_HIF_REMAP_L2 0xf11b0 793e57b7901SRyder Lee #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 794e57b7901SRyder Lee #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 795e57b7901SRyder Lee #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 796cd4c314aSBo Jiao #define MT_HIF_REMAP_L2_MT7916 0x1b8 797cd4c314aSBo Jiao #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16) 798cd4c314aSBo Jiao #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0) 799cd4c314aSBo Jiao #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16) 800cd4c314aSBo Jiao #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000 801cd4c314aSBo Jiao 802cd4c314aSBo Jiao #define MT_INFRA_BASE 0x18000000 803cd4c314aSBo Jiao #define MT_WFSYS0_PHY_START 0x18400000 804cd4c314aSBo Jiao #define MT_WFSYS1_PHY_START 0x18800000 805cd4c314aSBo Jiao #define MT_WFSYS1_PHY_END 0x18bfffff 806cd4c314aSBo Jiao #define MT_CBTOP1_PHY_START 0x70000000 80799ad32a4SBo Jiao #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END) 808cd4c314aSBo Jiao #define MT_CBTOP2_PHY_START 0xf0000000 80999ad32a4SBo Jiao #define MT_INFRA_MCU_START 0x7c000000 81099ad32a4SBo Jiao #define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END) 81199ad32a4SBo Jiao #define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE) 81299ad32a4SBo Jiao 81399ad32a4SBo Jiao /* CONN INFRA CFG */ 81499ad32a4SBo Jiao #define MT_CONN_INFRA_BASE 0x18001000 81599ad32a4SBo Jiao #define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs)) 81699ad32a4SBo Jiao 81799ad32a4SBo Jiao #define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020) 81899ad32a4SBo Jiao 81999ad32a4SBo Jiao #define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030) 82099ad32a4SBo Jiao #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0) 82199ad32a4SBo Jiao #define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2) 82299ad32a4SBo Jiao 82399ad32a4SBo Jiao #define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380) 82499ad32a4SBo Jiao 82599ad32a4SBo Jiao #define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300) 82699ad32a4SBo Jiao #define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7) 82799ad32a4SBo Jiao #define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0) 82899ad32a4SBo Jiao 82999ad32a4SBo Jiao #define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200) 83099ad32a4SBo Jiao #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0) 83199ad32a4SBo Jiao 83299ad32a4SBo Jiao #define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540) 83399ad32a4SBo Jiao #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0) 83499ad32a4SBo Jiao 83599ad32a4SBo Jiao #define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544) 83699ad32a4SBo Jiao #define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31)) 83799ad32a4SBo Jiao #define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31)) 83899ad32a4SBo Jiao 83999ad32a4SBo Jiao #define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414) 84099ad32a4SBo Jiao #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0) 84199ad32a4SBo Jiao #define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5) 84299ad32a4SBo Jiao 84399ad32a4SBo Jiao /* AFE */ 84499ad32a4SBo Jiao #define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19)) 84599ad32a4SBo Jiao #define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs)) 84699ad32a4SBo Jiao 84799ad32a4SBo Jiao #define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00) 84899ad32a4SBo Jiao #define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04) 84999ad32a4SBo Jiao #define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08) 85099ad32a4SBo Jiao #define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c) 85199ad32a4SBo Jiao 85299ad32a4SBo Jiao #define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4) 85399ad32a4SBo Jiao #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0)) 85499ad32a4SBo Jiao #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \ 85599ad32a4SBo Jiao FIELD_PREP(GENMASK(14, 0), 0x7e4)) 85699ad32a4SBo Jiao #define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6) 85799ad32a4SBo Jiao #define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0) 85899ad32a4SBo Jiao #define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2) 85999ad32a4SBo Jiao #define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16) 86099ad32a4SBo Jiao #define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \ 86199ad32a4SBo Jiao MT_AFE_WPLL_CFG_MASK | \ 86299ad32a4SBo Jiao MT_AFE_MCU_WPLL_CFG_MASK | \ 86399ad32a4SBo Jiao MT_AFE_MCU_BPLL_CFG_MASK) 86499ad32a4SBo Jiao #define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \ 86599ad32a4SBo Jiao FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \ 86699ad32a4SBo Jiao FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \ 86799ad32a4SBo Jiao FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2)) 86899ad32a4SBo Jiao 86999ad32a4SBo Jiao #define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15) 87099ad32a4SBo Jiao #define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9) 87199ad32a4SBo Jiao 87299ad32a4SBo Jiao #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0) 87399ad32a4SBo Jiao #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21) 87499ad32a4SBo Jiao #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20) 87599ad32a4SBo Jiao #define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \ 87699ad32a4SBo Jiao MT_AFE_RG_WBG_EN_WPLL_UP_MASK) 877*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_WF4 BIT(29) 878*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_BT BIT(21) 879*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_WF3 BIT(20) 880*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_WF2 BIT(19) 881*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_WF1 BIT(18) 882*6bad146dSAlexander Couzens #define MT_AFE_RG_WBG_EN_TXCAL_WF0 BIT(17) 88399ad32a4SBo Jiao 88499ad32a4SBo Jiao #define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19)) 88599ad32a4SBo Jiao #define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs)) 88699ad32a4SBo Jiao 88799ad32a4SBo Jiao #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120) 88899ad32a4SBo Jiao 88999ad32a4SBo Jiao /* ADIE */ 89099ad32a4SBo Jiao #define MT_ADIE_CHIP_ID 0x02c 891b5509983SPeter Chiu #define MT_ADIE_VERSION_MASK GENMASK(15, 0) 89299ad32a4SBo Jiao #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 89399ad32a4SBo Jiao #define MT_ADIE_IDX0 GENMASK(15, 0) 89499ad32a4SBo Jiao #define MT_ADIE_IDX1 GENMASK(31, 16) 89599ad32a4SBo Jiao 89699ad32a4SBo Jiao #define MT_ADIE_RG_TOP_THADC_BG 0x034 89799ad32a4SBo Jiao #define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12) 89899ad32a4SBo Jiao #define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3) 89999ad32a4SBo Jiao 90099ad32a4SBo Jiao #define MT_ADIE_RG_TOP_THADC 0x038 90199ad32a4SBo Jiao #define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23) 90299ad32a4SBo Jiao #define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0) 90399ad32a4SBo Jiao #define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26) 90499ad32a4SBo Jiao #define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5) 90599ad32a4SBo Jiao 90699ad32a4SBo Jiao #define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070 90799ad32a4SBo Jiao #define MT_ADIE_EFUSE_RDATA0 0x130 90899ad32a4SBo Jiao 90999ad32a4SBo Jiao #define MT_ADIE_EFUSE2_CTRL 0x148 91099ad32a4SBo Jiao #define MT_ADIE_EFUSE_CTRL_MASK BIT(1) 91199ad32a4SBo Jiao 91299ad32a4SBo Jiao #define MT_ADIE_EFUSE_CFG 0x144 91399ad32a4SBo Jiao #define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6) 91499ad32a4SBo Jiao #define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16) 91599ad32a4SBo Jiao #define MT_ADIE_EFUSE_VALID_MASK BIT(29) 91699ad32a4SBo Jiao #define MT_ADIE_EFUSE_KICK_MASK BIT(30) 91799ad32a4SBo Jiao 91899ad32a4SBo Jiao #define MT_ADIE_THADC_ANALOG 0x3a6 91999ad32a4SBo Jiao 92099ad32a4SBo Jiao #define MT_ADIE_THADC_SLOP 0x3a7 92199ad32a4SBo Jiao #define MT_ADIE_ANA_EN_MASK BIT(7) 92299ad32a4SBo Jiao 92399ad32a4SBo Jiao #define MT_ADIE_7975_XTAL_CAL 0x3a1 92499ad32a4SBo Jiao #define MT_ADIE_TRIM_MASK GENMASK(6, 0) 92599ad32a4SBo Jiao #define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0) 92699ad32a4SBo Jiao #define MT_ADIE_XO_TRIM_EN_MASK BIT(7) 92799ad32a4SBo Jiao #define MT_ADIE_XTAL_DECREASE_MASK BIT(6) 92899ad32a4SBo Jiao 92999ad32a4SBo Jiao #define MT_ADIE_7975_XO_TRIM2 0x3a2 93099ad32a4SBo Jiao #define MT_ADIE_7975_XO_TRIM3 0x3a3 93199ad32a4SBo Jiao #define MT_ADIE_7975_XO_TRIM4 0x3a4 93299ad32a4SBo Jiao #define MT_ADIE_7975_XTAL_EN 0x3a5 93399ad32a4SBo Jiao 93499ad32a4SBo Jiao #define MT_ADIE_XO_TRIM_FLOW 0x3ac 93599ad32a4SBo Jiao #define MT_ADIE_XTAL_AXM_80M_OSC 0x390 93699ad32a4SBo Jiao #define MT_ADIE_XTAL_AXM_40M_OSC 0x391 93799ad32a4SBo Jiao #define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398 93899ad32a4SBo Jiao #define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399 93999ad32a4SBo Jiao #define MT_ADIE_WRI_CK_SEL 0x4ac 94099ad32a4SBo Jiao #define MT_ADIE_RG_STRAP_PIN_IN 0x4fc 94199ad32a4SBo Jiao #define MT_ADIE_XTAL_C1 0x654 94299ad32a4SBo Jiao #define MT_ADIE_XTAL_C2 0x658 94399ad32a4SBo Jiao #define MT_ADIE_RG_XO_01 0x65c 94499ad32a4SBo Jiao #define MT_ADIE_RG_XO_03 0x664 94599ad32a4SBo Jiao 94699ad32a4SBo Jiao #define MT_ADIE_CLK_EN 0xa00 94799ad32a4SBo Jiao 94899ad32a4SBo Jiao #define MT_ADIE_7975_XTAL 0xa18 94999ad32a4SBo Jiao #define MT_ADIE_7975_XTAL_EN_MASK BIT(29) 95099ad32a4SBo Jiao 95199ad32a4SBo Jiao #define MT_ADIE_7975_COCLK 0xa1c 95299ad32a4SBo Jiao #define MT_ADIE_7975_XO_2 0xa84 95399ad32a4SBo Jiao #define MT_ADIE_7975_XO_2_FIX_EN BIT(31) 95499ad32a4SBo Jiao 95599ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL2 0xa94 95699ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20) 95799ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12) 95899ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \ 95999ad32a4SBo Jiao MT_ADIE_7975_XO_CTRL2_C2_MASK) 96099ad32a4SBo Jiao 96199ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL6 0xaa4 96299ad32a4SBo Jiao #define MT_ADIE_7975_XO_CTRL6_MASK BIT(16) 96399ad32a4SBo Jiao 96499ad32a4SBo Jiao /* TOP SPI */ 96599ad32a4SBo Jiao #define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19)) 96699ad32a4SBo Jiao #define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs)) 96799ad32a4SBo Jiao 96899ad32a4SBo Jiao #define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0) 96999ad32a4SBo Jiao #define MT_TOP_SPI_POLLING_BIT BIT(5) 97099ad32a4SBo Jiao 97199ad32a4SBo Jiao #define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50) 97299ad32a4SBo Jiao #define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15)) 97399ad32a4SBo Jiao #define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15)) 97499ad32a4SBo Jiao 97599ad32a4SBo Jiao #define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54) 97699ad32a4SBo Jiao #define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58) 97799ad32a4SBo Jiao 97899ad32a4SBo Jiao /* CONN INFRA CKGEN */ 97999ad32a4SBo Jiao #define MT_INFRA_CKGEN_BASE 0x18009000 98099ad32a4SBo Jiao #define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs)) 98199ad32a4SBo Jiao 98299ad32a4SBo Jiao #define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00) 98399ad32a4SBo Jiao #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23) 98499ad32a4SBo Jiao #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29) 98599ad32a4SBo Jiao 98699ad32a4SBo Jiao #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008) 98799ad32a4SBo Jiao #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c) 98899ad32a4SBo Jiao 98999ad32a4SBo Jiao #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040) 99099ad32a4SBo Jiao #define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2) 99199ad32a4SBo Jiao #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0) 99299ad32a4SBo Jiao 99399ad32a4SBo Jiao /* CONN INFRA BUS */ 99499ad32a4SBo Jiao #define MT_INFRA_BUS_BASE 0x1800e000 99599ad32a4SBo Jiao #define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs)) 99699ad32a4SBo Jiao 99799ad32a4SBo Jiao #define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300) 99899ad32a4SBo Jiao #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7) 99999ad32a4SBo Jiao #define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0) 100099ad32a4SBo Jiao 100199ad32a4SBo Jiao #define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c) 100299ad32a4SBo Jiao #define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360) 100399ad32a4SBo Jiao #define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364) 100499ad32a4SBo Jiao 100599ad32a4SBo Jiao /* CONN_INFRA_SKU */ 100699ad32a4SBo Jiao #define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000 100799ad32a4SBo Jiao #define MT_CONNINFRA_SKU_MASK GENMASK(15, 0) 100899ad32a4SBo Jiao #define MT_ADIE_TYPE_MASK BIT(1) 1009cd4c314aSBo Jiao 1010cd4c314aSBo Jiao /* FW MODE SYNC */ 10114dbcb912SRyder Lee #define MT_FW_ASSERT_STAT __REG(FW_ASSERT_STAT_ADDR) 10124dbcb912SRyder Lee #define MT_FW_EXCEPT_TYPE __REG(FW_EXCEPT_TYPE_ADDR) 10134dbcb912SRyder Lee #define MT_FW_EXCEPT_COUNT __REG(FW_EXCEPT_COUNT_ADDR) 10144dbcb912SRyder Lee #define MT_FW_CIRQ_COUNT __REG(FW_CIRQ_COUNT_ADDR) 10154dbcb912SRyder Lee #define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR) 10164dbcb912SRyder Lee #define MT_FW_CIRQ_LISR __REG(FW_CIRQ_LISR_ADDR) 10174dbcb912SRyder Lee #define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR) 10184dbcb912SRyder Lee #define MT_FW_TASK_IDX __REG(FW_TASK_IDX_ADDR) 10194dbcb912SRyder Lee #define MT_FW_TASK_QID1 __REG(FW_TASK_QID1_ADDR) 10204dbcb912SRyder Lee #define MT_FW_TASK_QID2 __REG(FW_TASK_QID2_ADDR) 10214dbcb912SRyder Lee #define MT_FW_TASK_START __REG(FW_TASK_START_ADDR) 10224dbcb912SRyder Lee #define MT_FW_TASK_END __REG(FW_TASK_END_ADDR) 10234dbcb912SRyder Lee #define MT_FW_TASK_SIZE __REG(FW_TASK_SIZE_ADDR) 10244dbcb912SRyder Lee #define MT_FW_LAST_MSG_ID __REG(FW_LAST_MSG_ID_ADDR) 10254dbcb912SRyder Lee #define MT_FW_EINT_INFO __REG(FW_EINT_INFO_ADDR) 10264dbcb912SRyder Lee #define MT_FW_SCHED_INFO __REG(FW_SCHED_INFO_ADDR) 102764d60725SRyder Lee 1028bdd2ca78SRyder Lee #define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR) 1029bdd2ca78SRyder Lee 1030bdd2ca78SRyder Lee #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 1031bdd2ca78SRyder Lee #define MT_SWDEF_MODE MT_SWDEF(0x3c) 1032cd4c314aSBo Jiao #define MT_SWDEF_NORMAL_MODE 0 1033cd4c314aSBo Jiao #define MT_SWDEF_ICAP_MODE 1 1034cd4c314aSBo Jiao #define MT_SWDEF_SPECTRUM_MODE 2 1035e57b7901SRyder Lee 1036bdd2ca78SRyder Lee #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 1037bdd2ca78SRyder Lee #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 1038bdd2ca78SRyder Lee #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 1039bdd2ca78SRyder Lee #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C) 1040bdd2ca78SRyder Lee #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 1041bdd2ca78SRyder Lee #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 1042bdd2ca78SRyder Lee #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 1043bdd2ca78SRyder Lee #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C) 1044bdd2ca78SRyder Lee #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060) 1045bdd2ca78SRyder Lee #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064) 1046bdd2ca78SRyder Lee 104790f5daeaSShayne Chen #define MT_DIC_CMD_REG_BASE 0x41f000 104890f5daeaSShayne Chen #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) 104990f5daeaSShayne Chen #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) 105090f5daeaSShayne Chen 105190f5daeaSShayne Chen #define MT_CPU_UTIL_BASE 0x41f030 105290f5daeaSShayne Chen #define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs)) 105390f5daeaSShayne Chen #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00) 105490f5daeaSShayne Chen #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04) 105590f5daeaSShayne Chen #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08) 105690f5daeaSShayne Chen #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c) 105790f5daeaSShayne Chen #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c) 105890f5daeaSShayne Chen 1059cd4c314aSBo Jiao /* LED */ 10600421bf80SMeiChia Chiu #define MT_LED_TOP_BASE 0x18013000 10610421bf80SMeiChia Chiu #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 10620421bf80SMeiChia Chiu 10630421bf80SMeiChia Chiu #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 10640421bf80SMeiChia Chiu #define MT_LED_CTRL_KICK BIT(7) 10659e81c2c7SLorenzo Bianconi #define MT_LED_CTRL_BAND BIT(4) 10660421bf80SMeiChia Chiu #define MT_LED_CTRL_BLINK_MODE BIT(2) 10670421bf80SMeiChia Chiu #define MT_LED_CTRL_POLARITY BIT(1) 10680421bf80SMeiChia Chiu 10690421bf80SMeiChia Chiu #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 10700421bf80SMeiChia Chiu #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 10710421bf80SMeiChia Chiu #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 10720421bf80SMeiChia Chiu 10739e81c2c7SLorenzo Bianconi #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x20 + ((_n) * 8)) 10749e81c2c7SLorenzo Bianconi #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x24 + ((_n) * 8)) 10759e81c2c7SLorenzo Bianconi #define MT_LED_STATUS_OFF GENMASK(31, 24) 10769e81c2c7SLorenzo Bianconi #define MT_LED_STATUS_ON GENMASK(23, 16) 10779e81c2c7SLorenzo Bianconi #define MT_LED_STATUS_DURATION GENMASK(15, 0) 10789e81c2c7SLorenzo Bianconi 10790421bf80SMeiChia Chiu #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 10800421bf80SMeiChia Chiu 10819e81c2c7SLorenzo Bianconi #define MT_LED_GPIO_MUX0 0x70005050 /* GPIO 1 and GPIO 2 */ 10829e81c2c7SLorenzo Bianconi #define MT_LED_GPIO_MUX1 0x70005054 /* GPIO 14 and 15 */ 1083cd4c314aSBo Jiao #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 10849e81c2c7SLorenzo Bianconi #define MT_LED_GPIO_MUX3 0x7000505c /* GPIO 26 */ 1085cd4c314aSBo Jiao 1086cd4c314aSBo Jiao /* MT TOP */ 1087e57b7901SRyder Lee #define MT_TOP_BASE 0x18060000 1088e57b7901SRyder Lee #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 1089e57b7901SRyder Lee 10901c7393e6SBo Jiao #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 1091e57b7901SRyder Lee #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 1092e57b7901SRyder Lee #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 109371bb496cSFelix Fietkau #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 1094e57b7901SRyder Lee 10951c7393e6SBo Jiao #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 10961c7393e6SBo Jiao #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 10971c7393e6SBo Jiao 1098e57b7901SRyder Lee #define MT_TOP_MISC MT_TOP(0xf0) 1099e57b7901SRyder Lee #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 1100e57b7901SRyder Lee 110199ad32a4SBo Jiao #define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4) 110299ad32a4SBo Jiao #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0) 110399ad32a4SBo Jiao 110499ad32a4SBo Jiao #define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4) 110599ad32a4SBo Jiao #define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0) 110699ad32a4SBo Jiao 1107*6bad146dSAlexander Couzens #define MT_TOP_WF_AP_PERI_BASE MT_TOP(0x1c8) 1108*6bad146dSAlexander Couzens #define MT_TOP_WF_AP_PERI_BASE_MASK GENMASK(19, 0) 1109*6bad146dSAlexander Couzens 1110*6bad146dSAlexander Couzens #define MT_TOP_EFUSE_BASE MT_TOP(0x1cc) 1111*6bad146dSAlexander Couzens #define MT_TOP_EFUSE_BASE_MASK GENMASK(19, 0) 1112*6bad146dSAlexander Couzens 111399ad32a4SBo Jiao #define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0) 111499ad32a4SBo Jiao #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0) 111599ad32a4SBo Jiao 111699ad32a4SBo Jiao #define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc) 111799ad32a4SBo Jiao #define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30) 111899ad32a4SBo Jiao 111999ad32a4SBo Jiao /* SEMA */ 112099ad32a4SBo Jiao #define MT_SEMA_BASE 0x18070000 112199ad32a4SBo Jiao #define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs)) 112299ad32a4SBo Jiao 112399ad32a4SBo Jiao #define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4)) 112499ad32a4SBo Jiao #define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4)) 112599ad32a4SBo Jiao #define MT_SEMA_RFSPI_STATUS_MASK BIT(1) 112699ad32a4SBo Jiao 112799ad32a4SBo Jiao /* MCU BUS */ 112899ad32a4SBo Jiao #define MT_MCU_BUS_BASE 0x18400000 112999ad32a4SBo Jiao #define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs)) 113099ad32a4SBo Jiao 113199ad32a4SBo Jiao #define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440) 113299ad32a4SBo Jiao #define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0) 113399ad32a4SBo Jiao #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28) 113499ad32a4SBo Jiao #define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31) 113599ad32a4SBo Jiao 113699ad32a4SBo Jiao #define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120) 113799ad32a4SBo Jiao 113899ad32a4SBo Jiao /* TOP CFG */ 113999ad32a4SBo Jiao #define MT_TOP_CFG_BASE 0x184b0000 114099ad32a4SBo Jiao #define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs)) 114199ad32a4SBo Jiao 114299ad32a4SBo Jiao #define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010) 114399ad32a4SBo Jiao 114499ad32a4SBo Jiao /* TOP CFG ON */ 114599ad32a4SBo Jiao #define MT_TOP_CFG_ON_BASE 0x184c1000 114699ad32a4SBo Jiao #define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs)) 114799ad32a4SBo Jiao 114899ad32a4SBo Jiao #define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604) 114999ad32a4SBo Jiao 115099ad32a4SBo Jiao /* SLP CTRL */ 115199ad32a4SBo Jiao #define MT_SLP_BASE 0x184c3000 115299ad32a4SBo Jiao #define MT_SLP(ofs) (MT_SLP_BASE + (ofs)) 115399ad32a4SBo Jiao 115499ad32a4SBo Jiao #define MT_SLP_STATUS MT_SLP(0x00c) 115599ad32a4SBo Jiao #define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23)) 115699ad32a4SBo Jiao #define MT_SLP_CTRL_EN_MASK BIT(0) 115799ad32a4SBo Jiao #define MT_SLP_CTRL_BSY_MASK BIT(1) 115899ad32a4SBo Jiao 115999ad32a4SBo Jiao /* MCU BUS DBG */ 116099ad32a4SBo Jiao #define MT_MCU_BUS_DBG_BASE 0x18500000 116199ad32a4SBo Jiao #define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs)) 116299ad32a4SBo Jiao 116399ad32a4SBo Jiao #define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0) 116499ad32a4SBo Jiao #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16) 116599ad32a4SBo Jiao #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3) 116699ad32a4SBo Jiao #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2) 116799ad32a4SBo Jiao 116864d60725SRyder Lee #define MT_HW_BOUND 0x70010020 116964d60725SRyder Lee #define MT_HW_REV 0x70010204 117064d60725SRyder Lee #define MT_WF_SUBSYS_RST 0x70002600 117164d60725SRyder Lee 1172cd4c314aSBo Jiao /* PCIE MAC */ 1173e57b7901SRyder Lee #define MT_PCIE_MAC_BASE 0x74030000 1174e57b7901SRyder Lee #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 1175e57b7901SRyder Lee #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 1176e57b7901SRyder Lee 1177cd4c314aSBo Jiao #define MT_PCIE1_MAC_INT_ENABLE 0x74020188 1178cd4c314aSBo Jiao #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188 1179cd4c314aSBo Jiao 118064d60725SRyder Lee #define MT_WM_MCU_PC 0x7c060204 118164d60725SRyder Lee #define MT_WA_MCU_PC 0x7c06020c 118264d60725SRyder Lee 1183aa79fe87SBo Jiao /* PP TOP */ 1184aa79fe87SBo Jiao #define MT_WF_PP_TOP_BASE 0x820cc000 1185aa79fe87SBo Jiao #define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs)) 1186aa79fe87SBo Jiao 1187aa79fe87SBo Jiao #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8) 1188aa79fe87SBo Jiao #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6) 1189aa79fe87SBo Jiao 1190cef37c78SBo Jiao #define MT_WF_IRPI_BASE 0x83000000 1191cef37c78SBo Jiao #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs)) 119299849398SRyder Lee 1193cef37c78SBo Jiao #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) 1194cef37c78SBo Jiao #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) 1195cef37c78SBo Jiao 1196cef37c78SBo Jiao /* PHY */ 1197e57b7901SRyder Lee #define MT_WF_PHY_BASE 0x83080000 1198e57b7901SRyder Lee #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 1199e57b7901SRyder Lee 1200e57b7901SRyder Lee #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) 1201cef37c78SBo Jiao #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20)) 120299849398SRyder Lee #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) 1203e57b7901SRyder Lee #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 1204e57b7901SRyder Lee 120599849398SRyder Lee #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) 1206cef37c78SBo Jiao #define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20)) 120799849398SRyder Lee #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 120899849398SRyder Lee #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) 120999849398SRyder Lee 1210bd2404d4SRyder Lee #define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16)) 1211bd2404d4SRyder Lee #define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20)) 1212bd2404d4SRyder Lee #define MT_WF_PHY_TPC_POWER GENMASK(15, 8) 1213bd2404d4SRyder Lee 121490f5daeaSShayne Chen #define MT_MCU_WM_CIRQ_BASE 0x89010000 121590f5daeaSShayne Chen #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) 121690f5daeaSShayne Chen #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) 121790f5daeaSShayne Chen #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0) 1218b662b71aSRyder Lee #define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x108) 1219b662b71aSRyder Lee #define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR MT_MCU_WM_CIRQ(0x118) 122090f5daeaSShayne Chen 1221e57b7901SRyder Lee #endif 1222