| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
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| H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
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| H A D | phy-qcom-qmp-pcs-ufs-v4.h | 10 #define QPHY_V4_PCS_UFS_PHY_START 0x000
11 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V4_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
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| H A D | phy-qcom-qmp-pcs-ufs-v5.h | 11 #define QPHY_V5_PCS_UFS_PHY_START 0x000
12 #define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
13 #define QPHY_V5_PCS_UFS_SW_RESET 0x008
14 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
15 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
16 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
17 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
18 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19 #define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
20 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
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| H A D | phy-qcom-qmp-qserdes-txrx-v4_20.h | 10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
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| /openbmc/linux/Documentation/RCU/ |
| H A D | lockdep-splat.rst | 30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]
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| /openbmc/qemu/tests/tcg/s390x/ |
| H A D | lpswe-early.S | 6 .org 0x8d
8 .org 0x8e
10 .org 0x150
12 .org 0x1D0 /* program new PSW */
13 .quad 0,pgm
14 .org 0x200 /* lowcore padding */
22 chhsi program_interruption_code,0x6 /* specification exception? */
24 cli ilc,0 /* ilc zero? */
34 .quad 0x8000000000000000,0xfedcba9876543210 /* bit 0 set */
36 .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
[all …]
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| H A D | stosm-early.S | 6 .org 0x8d
8 .org 0x8e
10 .org 0x150
12 .org 0x1D0 /* program new PSW */
13 .quad 0,pgm
14 .org 0x200 /* lowcore padding */
18 stosm ssm_op,0x10 /* bit 3 set */
23 chhsi program_interruption_code,0x6 /* specification exception? */
34 .byte 0
37 .quad 0x1000000180000000,expected_pswa /* bit 3 set */
[all …]
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| H A D | ssm-early.S | 6 .org 0x8d
8 .org 0x8e
10 .org 0x150
12 .org 0x1D0 /* program new PSW */
13 .quad 0,pgm
14 .org 0x200 /* lowcore padding */
23 chhsi program_interruption_code,0x6 /* specification exception? */
34 .byte 0x20 /* bit 2 set */
37 .quad 0x2000000180000000,expected_pswa /* bit 2 set */
39 .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
[all …]
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| H A D | exrl-ssm-early.S | 6 .org 0x8d
8 .org 0x8e
10 .org 0x150
12 .org 0x1D0 /* program new PSW */
13 .quad 0,pgm
14 .org 0x200 /* lowcore padding */
25 chhsi program_interruption_code,0x6 /* specification exception? */
36 .byte 0x08 /* bit 4 set */
39 .quad 0x0800000180000000,expected_pswa /* bit 2 set */
41 .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
[all …]
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| H A D | pgm-specification-softmmu.S | 7 .org 0x8d
9 .org 0x8e
11 .org 0x150
13 .org 0x1D0 /* program new PSW */
14 .quad 0x180000000,pgm /* 64-bit mode */
15 .org 0x200 /* lowcore padding */
22 chhsi program_interruption_code,0x6 /* PGM_SPECIFICATION? */
36 .quad 0x180000000,test /* 64-bit mode */
38 .quad 0x2000180000000,0xfff /* see is_special_wait_psw() */
40 .quad 0x2000180000000,0 /* disabled wait */
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| H A D | mc.S | 1 .org 0x8d
3 .org 0x8e
5 .org 0x94
7 .org 0xb0
9 .org 0x150
11 .org 0x1d0 /* program new PSW */
12 .quad 0x180000000,pgm /* 64-bit mode */
13 .org 0x200 /* lowcore padding */
17 mvhhi c8+6,0x4000
20 mc 123,0
[all …]
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| H A D | per.S | 1 .org 0x8d
3 .org 0x8e
5 .org 0x96
7 .org 0x98
9 .org 0x150
11 .org 0x1d0
13 .quad 0, pgm_handler
15 .org 0x200 /* exit lowcore */
18 .quad 0x4000000000000000, start_per
20 .quad 0x80000000, 0, -1 /* successful-branching everywhere */
[all …]
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| /openbmc/linux/drivers/clk/mstar/ |
| H A D | clk-msc313-cpupll.c | 17 * 0x140 -- LPF low. Seems to store one half of the clock transition
18 * 0x144 /
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
20 * 0x14c /
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
[all …]
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
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| H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
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| /openbmc/linux/drivers/tty/serial/8250/ |
| H A D | 8250_boca.c | 13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
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| /openbmc/qemu/include/hw/misc/ |
| H A D | sifive_e_aon.h | 28 #define SIFIVE_E_AON_WDOGKEY (0x51F15E)
29 #define SIFIVE_E_AON_WDOGFEED (0xD09F00D)
33 SIFIVE_E_AON_WDT = 0x0,
34 SIFIVE_E_AON_RTC = 0x40,
35 SIFIVE_E_AON_LFROSC = 0x70,
36 SIFIVE_E_AON_BACKUP = 0x80,
37 SIFIVE_E_AON_PMU = 0x100,
38 SIFIVE_E_AON_MAX = 0x150
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| /openbmc/linux/Documentation/fault-injection/ |
| H A D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | usb.h | 12 /* 0x000 */
18 /* 0x010 */
23 /* 0x020 */
26 /* 0x100 */
33 /* 0x120 */
39 /* 0x130 */
42 /* 0x140 */
48 /* 0x150 */
54 /* 0x160 */
60 /* 0x170 */
[all …]
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5_matrix.h | 13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
16 u32 res1[20]; /* 0x100 ~ 0x14c */
17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
20 u32 mesr; /* 0x15c: Master Error Status Register */
21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
22 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
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| /openbmc/linux/arch/arm/mach-davinci/ |
| H A D | clock.h | 13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | r8a774b1-cpg-mssr.c | 97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | hpet.h | 9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
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| /openbmc/linux/drivers/media/rc/keymaps/ |
| H A D | rc-x96max.c | 13 { 0x140, KEY_POWER },
22 { 0x118, KEY_VOLUMEUP },
23 { 0x110, KEY_VOLUMEDOWN },
25 { 0x143, KEY_MUTE }, // config
27 { 0x100, KEY_EPG }, // mouse
28 { 0x119, KEY_BACK },
30 { 0x116, KEY_UP },
31 { 0x151, KEY_LEFT },
32 { 0x150, KEY_RIGHT },
33 { 0x11a, KEY_DOWN },
[all …]
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