/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/ |
H A D | usb_init.c | 30 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch() 33 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); in mt76x2u_power_on_rf_patch() 34 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch() 36 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f); in mt76x2u_power_on_rf_patch() 39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch() 42 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); in mt76x2u_power_on_rf_patch() 45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch() 50 int shift = unit ? 8 : 0; in mt76x2u_power_on_rf() 54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf() 58 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | am335x-draco.dts | 45 reg = <0x4b000000 1000000>; 53 pinctrl-0 = <&gpio_mux_pins>; 57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */ 58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */ 59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */ 60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */ 61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */ 67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/ 68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */ [all …]
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H A D | vf610-pinfunc.h | 18 #define ALT0 0x0 19 #define ALT1 0x1 20 #define ALT2 0x2 21 #define ALT3 0x3 22 #define ALT4 0x4 23 #define ALT5 0x5 24 #define ALT6 0x6 25 #define ALT7 0x7 28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 #define QSERDES_V4_TX_BIST_INVERT 0x004 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19 #define QSERDES_V4_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 #define QSERDES_V5_TX_BIST_INVERT 0x004 13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 #define QSERDES_V5_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-pcs-ufs-v2.h | 9 #define QPHY_V2_PCS_UFS_PHY_START 0x000 10 #define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034 13 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038 14 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c 15 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040 17 #define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc 18 #define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c 19 #define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140 20 #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148 [all …]
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H A D | phy-qcom-qmp-pcs-ufs-v4.h | 10 #define QPHY_V4_PCS_UFS_PHY_START 0x000 11 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V4_PCS_UFS_SW_RESET 0x008 13 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 14 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 15 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 16 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 17 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 18 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 19 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v6_20.h | 9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac 12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80 16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c 18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v6.h | 11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00 12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04 13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10 14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14 15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18 16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c 17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20 18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24 19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28 20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c [all …]
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | st,stm32-rproc.yaml | 168 reg = <0x10000000 0x40000>, 169 <0x30000000 0x40000>, 170 <0x38000000 0x10000>; 174 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 182 reg = <0x10000000 0x40000>, 183 <0x30000000 0x40000>, 184 <0x38000000 0x10000>; 188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | fuse.h | 12 u32 reserved0[64]; /* 0x00 - 0xFC: */ 13 u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ 14 u32 reserved1[3]; /* 0x104 - 0x10c: */ 15 u32 sku_info; /* 0x110 */ 16 u32 reserved2[13]; /* 0x114 - 0x144: */ 17 u32 fa; /* 0x148: FUSE_FA */ 18 u32 reserved3[21]; /* 0x14C - 0x19C: */ 19 u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
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/openbmc/linux/drivers/clk/mstar/ |
H A D | clk-msc313-cpupll.c | 17 * 0x140 -- LPF low. Seems to store one half of the clock transition 18 * 0x144 / 19 * 0x148 -- LPF high. Seems to store one half of the clock transition 20 * 0x14c / 21 * 0x150 -- vendor code says "toggle lpf enable" 22 * 0x154 -- mu? 23 * 0x15c -- lpf_update_count? 24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? 25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to 27 * 0x174 -- Seems to be the PLL lock status bit [all …]
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/openbmc/linux/drivers/tty/serial/8250/ |
H A D | 8250_boca.c | 13 SERIAL8250_PORT(0x100, 12), 14 SERIAL8250_PORT(0x108, 12), 15 SERIAL8250_PORT(0x110, 12), 16 SERIAL8250_PORT(0x118, 12), 17 SERIAL8250_PORT(0x120, 12), 18 SERIAL8250_PORT(0x128, 12), 19 SERIAL8250_PORT(0x130, 12), 20 SERIAL8250_PORT(0x138, 12), 21 SERIAL8250_PORT(0x140, 12), 22 SERIAL8250_PORT(0x148, 12), [all …]
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/openbmc/linux/drivers/media/platform/mediatek/mdp3/ |
H A D | mdp_reg_rdma.h | 10 #define MDP_RDMA_EN 0x000 11 #define MDP_RDMA_RESET 0x008 12 #define MDP_RDMA_CON 0x020 13 #define MDP_RDMA_GMCIF_CON 0x028 14 #define MDP_RDMA_SRC_CON 0x030 15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068 17 #define MDP_RDMA_MF_SRC_SIZE 0x070 18 #define MDP_RDMA_MF_CLIP_SIZE 0x078 19 #define MDP_RDMA_MF_OFFSET_1 0x080 [all …]
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/openbmc/qemu/include/hw/timer/ |
H A D | nrf51_timer.h | 5 * + sysbus MMIO regions 0: GPIO registers 24 #define NRF51_TIMER_TASK_START 0x000 25 #define NRF51_TIMER_TASK_STOP 0x004 26 #define NRF51_TIMER_TASK_COUNT 0x008 27 #define NRF51_TIMER_TASK_CLEAR 0x00C 28 #define NRF51_TIMER_TASK_SHUTDOWN 0x010 29 #define NRF51_TIMER_TASK_CAPTURE_0 0x040 30 #define NRF51_TIMER_TASK_CAPTURE_3 0x04C 32 #define NRF51_TIMER_EVENT_COMPARE_0 0x140 33 #define NRF51_TIMER_EVENT_COMPARE_1 0x144 [all …]
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/openbmc/linux/drivers/video/fbdev/ |
H A D | wm8505fb_regs.h | 15 * Color space select register, default value 0x1c 22 #define WMT_GOVR_COLORSPACE 0x1e4 28 #define WMT_GOVR_COLORSPACE1 0x30 30 #define WMT_GOVR_CONTRAST 0x1b8 31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */ 34 #define WMT_GOVR_FBADDR 0x90 35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */ 38 #define WMT_GOVR_XPAN 0xa4 39 #define WMT_GOVR_YPAN 0xa0 41 #define WMT_GOVR_XRES 0x98 [all …]
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/openbmc/linux/Documentation/fault-injection/ |
H A D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1 34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2 39 dump_stack+0x5c/0x7d 40 should_fail+0x148/0x170 41 nvme_should_fail+0x2f/0x50 [nvme_core] 42 nvme_process_cq+0xe7/0x1d0 [nvme] 43 nvme_irq+0x1e/0x40 [nvme] 44 __handle_irq_event_percpu+0x3a/0x190 45 handle_irq_event_percpu+0x30/0x70 46 handle_irq_event+0x36/0x60 [all …]
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/openbmc/linux/arch/arm/mach-davinci/ |
H A D | clock.h | 13 #define PLLCTL 0x100 14 #define PLLCTL_PLLEN BIT(0) 21 #define PLLM 0x110 22 #define PLLM_PLLM_MASK 0xff 24 #define PREDIV 0x114 25 #define PLLDIV1 0x118 26 #define PLLDIV2 0x11c 27 #define PLLDIV3 0x120 28 #define POSTDIV 0x128 29 #define BPDIV 0x12c [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | starfive,jh7110-pcie-phy.yaml | 20 const: 0 54 reg = <0x10210000 0x10000>; 55 #phy-cells = <0>; 56 starfive,sys-syscon = <&sys_syscon 0x18>; 57 starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
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/openbmc/linux/arch/mips/include/asm/ |
H A D | hpet.h | 9 #define HPET_ID 0x000 10 #define HPET_PERIOD 0x004 11 #define HPET_CFG 0x010 12 #define HPET_STATUS 0x020 13 #define HPET_COUNTER 0x0f0 15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n) 16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n) 17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n) 19 #define HPET_T0_IRS 0x001 20 #define HPET_T1_IRS 0x002 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/qemu/include/hw/misc/ |
H A D | npcm7xx_gcr.h | 33 * 2:0: CPU and DRAM clock frequency. 42 #define FUP_NORM_UART3 0 49 #define CKFRQ_SKIPINIT 0x000 50 #define CKFRQ_DEFAULT 0x111 56 #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
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/openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
H A D | clock-axg.h | 18 #define HHI_GP0_PLL_CNTL 0x40 19 #define HHI_GP0_PLL_CNTL2 0x44 20 #define HHI_GP0_PLL_CNTL3 0x48 21 #define HHI_GP0_PLL_CNTL4 0x4c 22 #define HHI_GP0_PLL_CNTL5 0x50 23 #define HHI_GP0_PLL_STS 0x54 24 #define HHI_GP0_PLL_CNTL1 0x58 25 #define HHI_HIFI_PLL_CNTL 0x80 26 #define HHI_HIFI_PLL_CNTL2 0x84 27 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40 20 #define HHI_GP0_PLL_CNTL2 0x44 21 #define HHI_GP0_PLL_CNTL3 0x48 22 #define HHI_GP0_PLL_CNTL4 0x4c 23 #define HHI_GP0_PLL_CNTL5 0x50 24 #define HHI_GP0_PLL_STS 0x54 25 #define HHI_GP0_PLL_CNTL1 0x58 26 #define HHI_HIFI_PLL_CNTL 0x80 27 #define HHI_HIFI_PLL_CNTL2 0x84 28 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/openbmc/linux/drivers/mmc/host/ |
H A D | sdhci-esdhc.h | 27 #define ESDHC_HOST_CONTROL_LE 0x20 34 #define ESDHC_PRSSTAT 0x24 35 #define ESDHC_CLOCK_GATE_OFF 0x00000080 36 #define ESDHC_CLOCK_STABLE 0x00000008 39 #define ESDHC_PROCTL 0x28 40 #define ESDHC_VOLT_SEL 0x00000400 41 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 42 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 43 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 44 #define ESDHC_HOST_CONTROL_RES 0x01 [all …]
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