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/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3128.c18 .reg = 0xe8,
19 .bit = 0,
20 .mask = 0x7
24 .reg = 0xe8,
26 .mask = 0x7
30 .reg = 0xe8,
32 .mask = 0x7
36 .reg = 0xe8,
38 .mask = 0x7
42 .reg = 0xd4,
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c96 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
101 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
275 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
276 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
277 * 0 0 1 0 Prohibited setting
278 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
[all …]
H A Dr8a7796-cpg-mssr.c96 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
101 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
248 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
249 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
250 * 0 0 1 0 Prohibited setting
251 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
252 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr8a774a1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
100 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
116 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a774e1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
100 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
117 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a7796-cpg-mssr.c83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
106 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
107 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
108 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
109 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
110 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
111 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
112 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
113 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
123 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a7795-cpg-mssr.c81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a774b1-cpg-mssr.c97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
H A Dr8a77965-cpg-mssr.c101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
/openbmc/openbmc/meta-nuvoton/recipes-bsp/images/npcm7xx-igps/
H A D0001-Adjust-paths-for-use-with-Bitbake.patch24 <offset>0</offset> <!-- offset in the header -->
35 - <offset format='FileSize' align='0x1000'>output_binaries/BootBlockAndHeader.bin</offset> …
37 + <offset format='FileSize' align='0x1000'>Poleg_bootblock.bin.full</offset> <!-- offs…
50 <offset>0x144</offset>
51 <size>0x4</size>
61 <offset>0x200</offset>
75 <offset>0x144</offset>
76 <size>0x4</size>
86 <offset>0x200</offset>
100 <offset>0x144</offset> <!-- offset in the header -->
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dkonica.c29 #define WHITEBAL_REG 0x01
30 #define BRIGHTNESS_REG 0x02
31 #define SHARPNESS_REG 0x03
32 #define CONTRAST_REG 0x04
33 #define SATURATION_REG 0x05
44 0x00 -> 176x144, cropped
45 0x01 -> 176x144, cropped
46 0x02 -> 176x144, cropped
47 0x03 -> 176x144, cropped
48 0x04 -> 176x144, binned
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-draco.dts45 reg = <0x4b000000 1000000>;
53 pinctrl-0 = <&gpio_mux_pins>;
57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */
58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */
59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */
60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */
61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */
67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/
68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */
[all …]
H A Dvf610-pinfunc.h18 #define ALT0 0x0
19 #define ALT1 0x1
20 #define ALT2 0x2
21 #define ALT3 0x3
22 #define ALT4 0x4
23 #define ALT5 0x5
24 #define ALT6 0x6
25 #define ALT7 0x7
28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A Dci_udc.h13 u32 usbcmd; /* 0x130 */
14 u32 usbsts; /* 0x134 */
16 u32 devaddr; /* 0x144 */
17 u32 epinitaddr; /* 0x148 */
19 u32 portsc; /* 0x174 */
20 u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
21 u32 hostpc1_devlc; /* 0x1b4 */
22 u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
23 u32 usbmode; /* 0x1f8 */
24 u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dfuse.h12 u32 reserved0[64]; /* 0x00 - 0xFC: */
13 u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
14 u32 reserved1[3]; /* 0x104 - 0x10c: */
15 u32 sku_info; /* 0x110 */
16 u32 reserved2[13]; /* 0x114 - 0x144: */
17 u32 fa; /* 0x148: FUSE_FA */
18 u32 reserved3[21]; /* 0x14C - 0x19C: */
19 u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml168 reg = <0x10000000 0x40000>,
169 <0x30000000 0x40000>,
170 <0x38000000 0x10000>;
174 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
182 reg = <0x10000000 0x40000>,
183 <0x30000000 0x40000>,
184 <0x38000000 0x10000>;
188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
[all …]
/openbmc/u-boot/configs/
H A Dqemu-x86_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
52 CONFIG_FRAMEBUFFER_VESA_MODE=0x144
H A Dqemu-x86_64_defconfig2 CONFIG_SYS_TEXT_BASE=0x1110000
5 CONFIG_SYS_MALLOC_F_LEN=0x1000
9 CONFIG_DEBUG_UART_BASE=0x3f8
72 CONFIG_FRAMEBUFFER_VESA_MODE=0x144
/openbmc/linux/drivers/clk/mstar/
H A Dclk-msc313-cpupll.c17 * 0x140 -- LPF low. Seems to store one half of the clock transition
18 * 0x144 /
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
20 * 0x14c /
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
[all …]
/openbmc/qemu/include/hw/timer/
H A Dnrf51_timer.h5 * + sysbus MMIO regions 0: GPIO registers
24 #define NRF51_TIMER_TASK_START 0x000
25 #define NRF51_TIMER_TASK_STOP 0x004
26 #define NRF51_TIMER_TASK_COUNT 0x008
27 #define NRF51_TIMER_TASK_CLEAR 0x00C
28 #define NRF51_TIMER_TASK_SHUTDOWN 0x010
29 #define NRF51_TIMER_TASK_CAPTURE_0 0x040
30 #define NRF51_TIMER_TASK_CAPTURE_3 0x04C
32 #define NRF51_TIMER_EVENT_COMPARE_0 0x140
33 #define NRF51_TIMER_EVENT_COMPARE_1 0x144
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti.h22 * 0x000 - 0x144: CTI programming and status
23 * 0xEDC - 0xEF8: CTI integration test.
24 * 0xF00 - 0xFFC: Coresight management registers.
27 #define CTICONTROL 0x000
28 #define CTIINTACK 0x010
29 #define CTIAPPSET 0x014
30 #define CTIAPPCLEAR 0x018
31 #define CTIAPPPULSE 0x01C
32 #define CTIINEN(n) (0x020 + (4 * n))
33 #define CTIOUTEN(n) (0x0A0 + (4 * n))
[all …]
/openbmc/qemu/include/hw/char/
H A Dnrf51_uart.h20 #define UART_SIZE 0x1000
25 REG32(UART_STARTRX, 0x000)
26 REG32(UART_STOPRX, 0x004)
27 REG32(UART_STARTTX, 0x008)
28 REG32(UART_STOPTX, 0x00C)
29 REG32(UART_SUSPEND, 0x01C)
31 REG32(UART_CTS, 0x100)
32 REG32(UART_NCTS, 0x104)
33 REG32(UART_RXDRDY, 0x108)
34 REG32(UART_TXDRDY, 0x11C)
[all …]

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